11.7.13 Performance Monitors Component Identification Registers

There are four read-only Performance Monitors Component Identification Registers, Performance Monitors Component ID0 through Performance Monitors Component ID3. The following table shows these registers.

Table 11-19 Summary of the Performance Monitors Component Identification Registers

Register Value Offset
PMCIDR0 0x0D 0xFF0
PMCIDR1 0x90 0xFF4
PMCIDR2 0x05 0xFF8
PMCIDR3 0xB1 0xFFC
The Performance Monitors Component Identification Registers identify Performance Monitors as ARM PMUv3 architecture. The Component ID registers are:

Performance Monitors Component Identification Register 0

The PMCIDR0 characteristics are:

Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The PMCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR0 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMCIDR0 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMCIDR0 bit assignments.
Figure 11-14 PMCIDR0 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the PMCIDR0 bit assignments.

Table 11-20 PMCIDR0 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0
[7:0] PRMBL_0
0x0DPreamble byte 0
The PMCIDR0 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF0.

Performance Monitors Component Identification Register 1

The PMCIDR1 characteristics are:

Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The PMCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR1 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMCIDR1 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMCIDR1 bit assignments.
Figure 11-15 PMCIDR1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the PMCIDR1 bit assignments.

Table 11-21 PMCIDR1 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0
[7:4] CLASS
0x9Debug component
[3:0] PRMBL_1
0x0Preamble
The PMCIDR1 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF4.

Performance Monitors Component Identification Register 2

The PMCIDR2 characteristics are:

Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The PMCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR2 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMCIDR2 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMCIDR2 bit assignments.
Figure 11-16 PMCIDR2 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the PMCIDR2 bit assignments.

Table 11-22 PMCIDR2 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0
[7:0] PRMBL_2
0x05Preamble byte 2
The PMCIDR2 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFF8.

Performance Monitors Component Identification Register 3

The PMCIDR3 characteristics are:

Purpose
Provides information to identify a Performance Monitors component.
Usage constraints
The PMCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface.
The accessibility to the PMCIDR3 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
Table 11-1 External register access conditions describes the condition codes.
Configurations
The PMCIDR3 is in the Debug power domain.
Attributes
See the register summary in Table 11-7 Memory-mapped PMU register summary.
The following figure shows the PMCIDR3 bit assignments.
Figure 11-17 PMCIDR3 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the PMCIDR3 bit assignments.

Table 11-23 PMCIDR3 bit assignments

Bits Name Function
[31:8] -
Reserved, RES0
[7:0] PRMBL_3
0xB1Preamble byte 3
The PMCIDR3 can be accessed through the internal memory-mapped interface and the external debug interface, offset 0xFFC.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.