2.4.3 Power modes

The power domains can be controlled independently to give different combinations of powered-up and powered-down domains. However, only some powered-up and powered-down domain combinations are valid and supported.

The following table shows the valid powered-up and powered-down domain combinations for the different possible modes of operation. The table uses the following terms:
Off
Block is powered down.
WFx
Block is in WFI or WFE low-power state.
Ret
Logic or RAM retention power only.
On
Block is powered up.

Table 2-3 Valid power modes

Mode Corea (CLK) Debug APB, CTI, and CTM (PCLKDBG) L2 RAMsb (CLK) L2 control, GIC, Timer (CLK)
L2 control powerup and L2 RAMs powerup On | WFx | Ret | Off c Off | On On On
L2 control powerup and L2 RAMs retained WFx | Ret | Off d Off | On Ret On
L2 cache Dormant mode All Off Off | On On | Ret Off
PCLKDBG powerup All Off On Off Off
Processor shutdown All Off Off Off Off
There are specific requirements that you must meet to power up and power down each power domain within the core. The supported powerup and powerdown sequences are:

Note

  • The powerup and powerdown sequences in the following sections are the only power sequences that ARM recommends. Any deviation from these sequences can lead to unpredictable results.
  • The powerup and powerdown sequences require that you isolate the powerup domain before power is removed from the powerdown domain. You must clamp the outputs of the powerdown domain to benign values to prevent data corruption or unpredictable behavior in the powerup domain.
Related information
Dormant mode

Individual core powerdown

If an individual core is not required, you can reduce leakage power by turning off the power to the core. The core refers to all core logic, including Advanced SIMD and FP unit, L1 RAMs, Debug, ETM, breakpoint and watchpoint logic.

To enable the core to be powered down, the implementation must place the core on a separately controlled power supply. In addition, you must clamp the outputs of the core to benign values while the core is powered down.
To power down the core power domain, apply the following sequence:
  1. Clear the appropriate System Control Register C bit, data or unified cache enable, to prevent additional data cache allocation.
  2. Disable L2 prefetches by writing a one to bit [38] and zeros to bits[36:35, 33:32] of the CPU Extended Control Register.
  3. Disable the Load-store hardware prefetcher by writing a one to bit [56] of the CPU Auxiliary Control Register.
  4. Execute an ISB instruction to ensure the CPU Extended Control Register and CPU Auxiliary Control Register writes are complete.
  5. Execute a DSB instruction to ensure completion of any prior prefetch requests.
  6. Clean and invalidate all data from the L1 data cache. The L2 duplicate Snoop Tag RAM for this core is now empty. This prevents any new data cache snoops or data cache maintenance operations from other processors in the processor being issued to this core.
  7. Clear the CPUECTLR.SMPEN bit. Clearing the SMPEN bit enables the core to be taken out of coherency by preventing the core from receiving instruction cache, TLB, or BTB maintenance operations broadcast by other processors in the multiprocessor.
  8. Ensure that the system does not send interrupts to the core that is being powered down.
  9. Set the DBGOSDLR.DLK, Double lock control bit, that forces the debug interfaces to be quiescent.
  10. Execute an ISB instruction to ensure that all of the System register changes from the previous steps have been committed.
  11. Execute a DSB instruction to ensure that all instruction cache, TLB, and branch predictor maintenance operations issued by any core in the processor before the SMPEN bit was cleared have completed.
  12. Execute a WFI instruction and wait until the STANDBYWFI output asserts to indicate that the core is idle and in the WFI low-power state.
  13. Activate the core output clamps.
  14. Remove power from the core power domain.
To power up the core power domain, apply the following sequence:
  1. Assert nCPUPORESET.
  2. Apply power to the core power domain while keeping nCPUPORESET asserted. When power is restored, continue to hold nCPUPORESET for 16 CLK cycles to allow the reset to propagate.
  3. Release the core output clamps.
  4. Deassert nCPUPORESET.

Processor powerdown without system driven L2 flush

The Cortex-A72 processor supports processor powerdown where all the processor power domains are shut down and all state is lost. In this section, a lead core is defined as the last core to powerdown, or the first core to powerup.

To power down the processor, apply the following sequence:
  1. Ensure all non-lead processors are in shutdown mode, see Individual core powerdown.
  2. For the lead processor, follow steps 1 to 5 in Individual core powerdown.
  3. When ACP is present and all outstanding ACP transactions are complete, the SoC can assert AINACTS to idle the ACP. When AINACTS has been asserted, the SoC must not assert ARVALIDS, AWVALIDS, or WVALIDS.
  4. Clean and invalidate all data from the L2 data cache.
  5. If the core implements:
    An ACE interface
    When all outstanding snoop transactions are complete, the SoC can assert ACINACTM.
    A CHI interface
    When all outstanding snoop transactions are complete, the SoC can assert SINACT.
  6. Ensure system interrupts to the processor are disabled.
  7. Follow steps 7 to 14 in Individual core powerdown.
  8. Wait until STANDBYWFIL2 asserts to indicate that the L2 memory system is idle.
  9. Activate the output clamps of the processor in the SoC.
  10. Remove power from the L2 control and L2 RAM power domains.
To power up the Cortex-A72 processor, apply the following sequence:
  1. For each core in the MPCore device, assert nCPUPORESET LOW.
  2. For the lead core in the MPCore device, assert nPRESETDBG and nL2RESET LOW, and hold L2RSTDISABLE LOW.
  3. Apply power to the processor, L2 control, L2 RAM and debug power domains while keeping the signals described in steps 1 and 2 LOW.
  4. Release the output clamps of the processor in the SoC.
  5. Continue a normal powerup reset sequence.

Processor powerdown with system driven L2 flush

The Cortex-A72 processor supports processor powerdown where all the processor power domains are shut down and all state is lost. In this section, a lead processor is defined as the last core to powerdown, or the first core to powerup.

To power down the processor, apply the following sequence:
  1. Ensure all non-lead cores are in shutdown mode, see Individual core powerdown.
  2. For the lead core, follow steps 1 to 5 in Individual core powerdown.
  3. When ACP is present and all outstanding ACP transactions are complete, the SoC can assert AINACTS to idle the ACP. When AINACTS has been asserted, the SoC must not assert ARVALIDS, AWVALIDS, or WVALIDS.
  4. Ensure system interrupts to the processor are disabled.
  5. Follow steps 7 to 14 in Individual core powerdown.
  6. The SoC can now assert the L2FLUSHREQ input.
  7. The L2 performs a series of internal clean and invalidate operations to each set and way of the L2 cache.
  8. When the L2 completes the clean and invalidate sequence, it asserts the L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then the L2 deasserts L2FLUSHDONE.
  9. If the core implements:
    An ACE interface
    When all outstanding snoop transactions are complete, the SoC can assert ACINACTM to idle the AXI master interface. When ACINACTM has been asserted, the SoC must not assert ACVALIDM..
    A CHI interface
    When all outstanding snoop transactions are complete, the SoC can assert SINACT.
  10. Wait until STANDBYWFIL2 asserts to indicate that the L2 memory system is idle.
  11. Activate the output clamps of the processor in the SoC.
  12. Remove power from the L2 control and L2 RAM power domains.
To power up the Cortex-A72 processor, apply the following sequence:
  1. For each core in the MPCore device, assert nCPUPORESET LOW.
  2. For the lead core in the MPCore device, assert nPRESETDBG and nL2RESET LOW, and hold L2RSTDISABLE LOW.
  3. Apply power to the core, L2 control, L2 RAM and debug power domains while keeping the signals described in steps 1 and 2 LOW.
  4. Release the output clamps of the processor in the SoC.
  5. Continue a normal powerup reset sequence.

Dormant mode

The Cortex-A72 processor supports Dormant mode, where all the processors, debug PCLKDBG, and L2 control logic are powered down while the L2 cache RAMs are powered up and retain state.

This reduces the energy cost of writing dirty lines back to memory and improves response time on powerup. In Dormant mode, the L2 cache is not kept hardware coherent with other masters in the system.
The RAM blocks that remain powered up and retained during Dormant mode are:
  • L2 Tag RAMs.
  • L2 Dirty RAMs.
  • L2 Data RAMs.
  • L2 Inclusion PLRU RAMs.
To support Dormant mode, the L2 cache RAMs must be implemented in a separate power domain. In addition, you must clamp all inputs to the L2 cache RAMs to benign values, to avoid corrupting data when the processors and L2 control power domains enter and exit powerdown state.
Before entering Dormant mode, the architectural state of the processor, excluding the contents of the L2 cache RAMs that remain powered up, must be saved to external memory.
To exit from Dormant mode to Run mode, the SoC must perform a full powerup reset sequence. The SoC must assert the reset signals until power is restored. After power is restored, the processor exits the powerup reset sequence, and the architectural state must be restored.
To enter Dormant mode, apply the following sequence:
  1. Clear the appropriate System Control Register C bit, data or unified cache enable, to prevent additional data cache allocation.
  2. Clean and invalidate all data from the L1 data cache. The L2 duplicate Snoop Tag RAM for this core is now empty. This prevents any new data cache snoops or data cache maintenance operations from other processors in the processor being issued to this core.
  3. Clear the CPUECTLR.SMPEN bit. Clearing the SMPEN bit enables the core to be taken out of coherency by preventing the core from receiving instruction cache, TLB, or BTB maintenance operations broadcast by other processors in the MPCore device.
  4. Ensure that the system does not send interrupts to the core that is being powered down.
  5. Save architectural state, if required. These state saving operations must ensure that the following occur:
    • All ARM registers, including the core state, are saved.
    • All System registers are saved.
    • All debug related state is saved.
  6. Set the DBGOSDLR.DLK, Double lock control bit, that forces the debug interfaces to be quiescent.
  7. Execute an ISB instruction to ensure that all of the System register changes from the previous steps have been committed.
  8. Execute a DSB instruction to ensure that all instruction cache, TLB, and branch predictor maintenance operations issued by any core in the processor before the SMPEN bit was cleared have completed. In addition, this ensures that all state saving has completed.
  9. Execute a WFI instruction and wait until the STANDBYWFI output is asserted, to indicate that the core is in idle and low-power state.
  10. Repeat the previous steps for all processors, and wait for all STANDBYWFI outputs to assert.
  11. If the processor implements:
    An ACE interface
    When all outstanding snoop transactions are complete, the SoC asserts ACINACTM. When ACINACTM has been asserted, the SoC must not assert ACVALIDM.
    A CHI interface
    When all outstanding snoop transactions are complete, the SoC asserts SINACT.
    When ACP is present and all outstanding ACP transactions are complete, the SoC asserts AINACTS. When AINACTS has been asserted, the SoC must not assert ARVALIDS, AWVALIDS, or WVALIDS.
    When the L2 completes the outstanding transactions for the AXI, or CHI, interface then STANDBYWFIL2 asserts to indicate that the L2 memory system is idle.
  12. When all of the core STANDBYWFI signals and the STANDBYWFIL2 are asserted, the processor is ready to enter Dormant mode.
  13. Activate the L2 cache RAM input clamps.
  14. Remove power from the cores, debug PCLKDBG, and L2 control power domains.
To exit Dormant mode, apply the following sequence:
  1. Apply a normal powerup reset sequence. You must apply resets to the cores, debug PCLKDBG, and the L2 memory system logic until power is restored. During this reset sequence, L2RSTDISABLE must be held HIGH to disable the L2 cache hardware reset mechanism.
  2. When power is restored, release the L2 cache RAM input clamps.
  3. Continue a normal powerup reset sequence with L2RSTDISABLE held HIGH. The L2RSTDISABLE must be held HIGH for a minimum of 32 CLK cycles after the deasserting edge of nL2RESET.
  4. The architectural state must be restored, if required.

Debug powerdown

If the Cortex-A72 processor runs in an environment where debug facilities are not required for any of its cores then you can reduce leakage power by turning off the power to the debug unit in the PCLKDBG domain.

To enable the debug unit in the PCLKDBG domain to be powered down, the implementation must place the debug unit on a separately controlled power supply. In addition, you must clamp the outputs of the debug unit to benign values while the debug unit is powered down.
To power down the debug PCLKDBG power domain, apply the following sequence:
  1. Activate the debug output clamps.
  2. Remove power from the debug PCLKDBG domain.

Note

If the debug output clamps are released without following the specified debug powerup sequence, the results are unpredictable.
To power up the debug PCLKDBG power domain, apply the following sequence:
  1. Assert nPRESETDBG.
  2. Apply power to the debug PCLKDBG power domain while keeping nPRESETDBG asserted.
  3. Release the debug output clamps.
  4. If the SoC uses the debug hardware, deassert nPRESETDBG.

External debug over powerdown

The Cortex-A72 processor provides support for external debug over powerdown. If any or all of the cores are powered down, the SoC can still use the debug facilities if the debug PCLKDBG domain is powered up.

To enable external debug over powerdown, the implementation must place the core and the debug PCLKDBG unit on separately controlled power supplies. If the core is powered down while the debug PCLKDBG unit is powered up, you must clamp all outputs from the core power domain to the debug power domain to benign values.
To power down the core power domain for external debug over powerdown support, apply the following additional step to the core powerdown sequence, as described in Individual core powerdown, after STANDBYWFI is asserted in step 12, and before core clamps are activated in step 13:
  • Deassert DBGPWRDUP to indicate that the core debug resources are not available for APB accesses.
When power is removed from the core power domain, keep the debug PCLKDBG unit powered up.
To power up the core power domain after external debug over powerdown support is no longer required, apply the following additional step to the core powerup sequence, as described in Individual core powerdown, after nCPUPORESET is deasserted in step 5.
  • Assert DBGPWRDUP to indicate that processor debug resources are available.
a
Core, which includes the Advanced SIMD and FP, Debug, ETM, breakpoint and watchpoint (CLK) logic.
b
For L2 RAMs dynamic retention, the L2 Data, Dirty, Tag, Inclusion PLRU, and Snoop Tag RAMs are retained.
For L2 cache Dormant mode, the L2 Data, Dirty, Tag, and Inclusion PLRU RAMs are retained.
c
This power mode requires all the cores to be in one of On, WFI, WFE, Retention, or Off state. Each core can be in a different one of these states.
d
This power mode requires all the cores to be in one of WFI, WFE, Retention, or Off state. Each core can be in a different one of these states.
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