8.3.3 CPU interface System register descriptions

This section only describes registers whose implementation is specific to the Cortex-A72 processor. All other registers are described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3. Table 8-4 AArch64 GIC CPU interface System register summary provides cross-references to individual registers.

Active Priority Group0 Register

The ICC_AP0R0_EL1 characteristics are:
Purpose
Provides support for preserving and restoring state in power-management applications.
Usage constraints
Accessibility and constraints on this register are described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.
Configurations
Available if the GIC is implemented for System register mode.
Attributes
See the register summary in Table 8-4 AArch64 GIC CPU interface System register summary.
The multiprocessor implements the ICC_AP0R0_EL1 according to the recommendations described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.
The following table shows the Cortex-A72 MPCore processor ICC_AP0R0_EL1 implementation.

Table 8-7 Active Priority Group0 Register implementation

Number of group priority bits Preemption levels Minimum legal value of BPR Active Priority Group0 Registers implemented
5 32 2 ICC_AP0R0_EL1[31:0]

Active Priority Group1 Register

The ICC_AP1R0_EL1 characteristics are:
Purpose
Provides support for preserving and restoring state in power-management applications.
Usage constraints
This register is Banked to provide Secure and Non-secure copies. This ensures that Non-secure accesses do not interfere with Secure operation. Accessibility and constraints on this register are described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.
Configurations
Available if the GIC is implemented for System register mode.
Attributes
See the register summary in Table 8-4 AArch64 GIC CPU interface System register summary.
The multiprocessor implements the ICC_AP1R0_EL1 according to the recommendations described in the ARM® Generic Interrupt Controller Architecture Specification, GICv3.
The following table shows the Cortex-A72 processor ICC_AP1R0_EL1 implementation.

Table 8-8 Active Priority Group1 Register implementation

Number of group priority bits Preemption levels Minimum legal value of Secure BPR Minimum legal value of Non-secure BPR Active Priority Group1 Registers implemented
5 32 2 3 ICC_AP1R0_EL1[31:0]
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