8.3.1 CPU interface register summary

Each GIC CPU interface block provides the interface for a Cortex-A72 processor that operates with the GIC. Each CPU interface provides a programming interface for:
  • Enabling the signaling of interrupt requests by the CPU interface.
  • Acknowledging an interrupt.
  • Indicating completion of the processing of an interrupt.
  • Setting an interrupt priority mask for the core.
  • Defining the preemption policy for the core.
  • Determining the highest priority pending interrupt for the core.
For more information on CPU interfaces, see the ARM® Generic Interrupt Controller Architecture Specification, GICv3.

AArch32 GIC CPU interface memory-mapped register summary

The following table shows the GIC CPU interface register address offsets of the Cortex-A72 processor. For information about an external standalone GIC such as the ARM GIC-400 or other proprietary GIC, see the documentation of that product.

The following table shows the register memory map for the CPU interface in AArch32. The offsets in this table are relative to the CPU interface block base address as shown in Table 8-1 Cortex-A72 processor GIC memory map.
All the registers in the following table are word-accessible. Registers not described in this table are Reserved.

Table 8-2 GIC CPU interface memory-mapped register summary

Offset Name Type Reset Description
0x0000 GICC_CTLR RW 0x00000000 CPU Interface Control Register a
0x0004 GICC_PMR RW 0x00000000 Interrupt Priority Mask Register
0x0008 GICC_BPR RW
0x00000002 (S)b
0x00000003 (NS)c
Binary Point Register
0x000C GICC_IAR RO 0x000003FF Interrupt Acknowledge Register
0x0010 GICC_EOIR WO - End Of Interrupt Register
0x0014 GICC_RPR RO 0x000000FF Running Priority Register
0x0018 GICC_HPPIR RO 0x000003FF Highest Priority Pending Interrupt Register
0x001C GICC_ABPR RW 0x00000003 Aliased Binary Point Register
0x0020 GICC_AIAR RO 0x000003FF Aliased Interrupt Acknowledge Register
0x0024 GICC_AEOIR WO - Aliased End of Interrupt Register
0x0028 GICC_AHPPIR RO 0x000003FF Aliased Highest Priority Pending Interrupt Register
0x00D0 GICC_APR0 RW 0x00000000 Active Priority Register
0x00E0 GICC_NSAPR0 RW 0x00000000 Non-secure Active Priority Register
0x00FC GICC_IIDR RO 0x0084043B CPU Interface Identification Register
0x1000 GICC_DIR WO - Deactivate Interrupt Register

AArch32 GIC CPU interface System register summary

The following table shows the System register map for the CPU interface in AArch32. See the ARM® Generic Interrupt Controller Architecture Specification, GICv3 for more information about the registers.

Table 8-3 AArch32 GIC CPU interface System register summary

Name CRn op1 CRm op2 Type Description
ICC_PMR c4 0 c6 0 RW Priority Mask Register
ICC_IAR0 c12 0 c8 0 RO Group0 Interrupt Acknowledge Register
ICC_EOIR0     1 WO Group0 End of Interrupt Register
ICC_HPPIR0     2 RO Group0 Highest Priority Pending Interrupt Register
ICC_BPR0     3 RW Group0 Binary Pointer Register
ICC_AP0R0     4 RW Active Priority Group0 Register
ICC_AP1R0     c9 0 RW Active Priority Group1 Register
ICC_DIR     c11 1 WO Deactivate Register
ICC_RPR     3 RO Running Priority Register
ICC_IAR1     c12 0 RO Group1 Interrupt Acknowledge Register
ICC_EOIR1   1 WO Group1 End of Interrupt Register
ICC_HPPIR1   2 RO Group1 Highest Priority Pending Interrupt Register
ICC_BPR1   3 RW Bd Group1 Binary Pointer Register
ICC_CTLR   4 RW B Control Register
ICC_SRE   5 RW B System Register Enable
ICC_IGRPEN0   6 RW Group0 Interrupt Group Enable
ICC_IGRPEN1   7 RW B Group1 Interrupt Group Enable
ICC_SGI1Re   - WO Group1 Software Generated Interrupt Register
ICC_ASGI1R   0 c12 - WO Aliased Group1 Software Generated Interrupt Register
ICC_SGI0R   2 c12 - WO Group0 Software Generated Interrupt Register
ICC_MCTLR   6 c12 4 RW Monitor Control Register
ICC_MSRE     5 RW Monitor System Register Enable
ICC_MGRPEN1     7 RW Monitor Group1 Interrupt Group Enable

AArch64 GIC CPU interface System register summary

The following table shows the System register map for the GIC CPU interface in AArch64. See the ARM® Generic Interrupt Controller Architecture Specification, GICv3 for more information about the registers.

Table 8-4 AArch64 GIC CPU interface System register summary

Name Type Description
ICC_PMR_EL1 RW Priority Mask Register
ICC_IAR0_EL1 RO Group0 Interrupt Acknowledge Register
ICC_EOIR0_EL1 WO Group0 End of Interrupt Register
ICC_HPPIR0_EL1 RO Group0 Highest Priority Pending Interrupt Register
ICC_BPR0_EL1 RW Group0 Binary Pointer Register
ICC_AP0R0_EL1 RW Active Priority Group0 Register
ICC_AP1R0_EL1 RW Active Priority Group1 Register
     
ICC_DIR_EL1 WO Deactivate Register
ICC_RPR_EL1 RO Running Priority Register
ICC_SGI1R_EL1 WO Group1 Software Generated Interrupt Register
ICC_ASGI1R_EL1 WO Aliased Group1 Software Generated Interrupt Register
ICC_SGI0R_EL1 WO Group0 Software Generated Interrupt Register
ICC_IAR1_EL1 RO Group1 Interrupt Acknowledge Register
ICC_EOIR1_EL1 WO Group1 End of Interrupt Register
ICC_HPPIR1_EL1 RO Group1 Highest Priority Pending Interrupt Register
ICC_BPR1_EL1 RW Bf Group1 Binary Pointer Register
ICC_CTLR_EL1 RW B Control Register
ICC_SRE_EL1 RW B System Register Enable
ICC_IGRPEN0_EL1 RW Group0 Interrupt Group Enable Register
ICC_IGRPEN1_EL1 RW B Group1 Interrupt Group Enable
ICC_CTLR_EL3 RW EL3 Control Register
ICC_SRE_EL3 RW EL3 System Register Enable
ICC_GRPEN1_EL3 RW EL3 Group1 Interrupt Group Enable
a See the ARM® Generic Interrupt Controller Architecture Specification, GICv3 for more information.
b S = Secure.
c NS = Non-secure.
d When operating in EL3, accesses to Banked EL1 registers access the copy designated by the current value of the SCR_EL3.NS. When EL3 is using AArch32, there is no Secure EL1 interrupt regime and accesses in any Secure EL3 mode, except Monitor mode, access the Secure copy.
e Use MCRR instructions to access this register in AArch32 state.
f When operating in EL3, accesses to Banked EL1 registers access the copy designated by the current value of the SCR_EL3.NS. When EL3 is using AArch32, there is no Secure EL1 interrupt regime and accesses in any Secure EL3 mode, except Monitor mode, access the Secure copy.
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