3.4.2 Register description

This section describes the processor Jazelle Extension registers. The following table provides cross-references to individual registers.

Jazelle Identity Register

The JIDR characteristics are:
Purpose
Enables software to determine the implementation of the Jazelle Extension provided by the processor.
Usage constraints
The JIDR is:
  • A read-only register
  • Accessible from all Exception levels in AArch32.
Configurations
Available in all configurations.
Attributes
See the register summary in table Table 3-3 Summary of Jazelle registers.
The JIDR is a 32-bit register with all bits[31:0] as RES0. Writes are ignored, and all bits read as zero.
To access the JIDR in the AArch32 state, read the register with:
MRC p14, 7, <Rd>, c0, c0, 0; Read Jazelle Identity Register

Jazelle OS Control Register

The JOSCR characteristics are:
Purpose
Provides operating system control of the use of the Jazelle Extension.
Usage constraints
The JOSCR is:
  • A read/write register
  • Accessible only from EL1 or higher.
Configurations
Available in all configurations.
Attributes
See the register summary in table Table 3-3 Summary of Jazelle registers.
The JOSCR is a 32-bit register with all bits[31:0] as RES0. Writes are ignored, and all bits read as zero.
To access the JOSCR in the AArch32 state, read or write the register with:
MRC p14, 7, <Rd>, c1, c0, 0;  Read Jazelle OS Control Register
MCR p14, 7, <Rd>, c1, c0, 0;  Write Jazelle OS Control Register

Jazelle Main Configuration Register

The JMCR characteristics are:

Purpose
Provides control of the Jazelle Extension features.
Usage constraints
The JMCR is:
  • A read/write register
  • Accessible only from EL1 or higher.
Configurations
Available in all configurations.
Attributes
See the register summary in table Table 3-3 Summary of Jazelle registers.
The JMCR is a 32-bit register with all bits[31:0] as RES0. Writes are ignored, and all bits read as zero.
To access the JMCR in the AArch32 state, read or write the register with:
MRC p14, 7, <Rd>, c2, c0, 0;  Read Jazelle Main Configuration Register
MCR p14, 7, <Rd>, c2, c0, 0;  Write Jazelle Main Configuration Register
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