The Load/store unit includes a hardware prefetcher that is responsible for generating prefetches targeting both the L1D cache and L2 cache.
Prefetching on loads
The load side prefetcher uses a hybrid mechanism which is based on both physical-address (PA) and virtual-address (VA) prefetching to either or both of the L1D cache and
L2 cache, depending on the memory access patterns.
Prefetching on stores
Prefetching on store accesses is managed by a PA based prefetcher and only prefetches
to the L2 cache.
The Load/Store HW prefetcher can be controlled in the following manner using
software programmable bits:
- Disable the Load/Store HW prefetcher:
The load/store HW prefetcher can be
disabled by setting the CPUACTLR_EL1 bit [56].
- Disable VA based prefetch:
Prefetching using VA can be disabled by setting
the CPUACTLR_EL1 bit [43]. When set, prefetch is restricted to within the
page boundary of the demand request triggering that triggers the
prefetch.
- Disable prefetch on store:
Prefetching on stores can be disabled by setting
the CPUACTLR_EL1 bit [42].
- Maximum load prefetch distance to L2:
You can control the maximum prefetch
distance to the L2, for load side prefetching, by programming bits [33:32]
of the CPUECTLR_EL1 register.
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