7.4 L2 cache prefetcher
The Cortex-A72 processor includes a hardware L2 prefetcher that handles prefetch generation for instruction fetch and TBW descriptor accesses.
NoteThe Load/store unit handles prefetch generation for Load/store accesses targeting both the L1D cache and L2 cache.
Some of the key features are:
You can program the CPUECTLR register to indicate the maximum number of prefetches to be
allocated in the PRQ on the following:
- An instruction fetch miss in the L2 cache by programming CPUECTLR_EL1[36:35].
The programmed distance is also used as the skip distance for any instruction
fetch read with a stride match that hits in the L2 cache. In these cases, a single prefetch
request is allocate in the PRQ as:
prefetch address = current address + (stride × programmed distance)
NoteThe stride for an instruction fetch access is always one cache line.