2.2.2 Optional Accelerator Coherency Port

The processor implements an optional Accelerator Coherency Port (ACP). This is an AMBA 4 AXI slave interface.

The ACP slave interface supports memory coherent accesses to the Cortex-A72 processor memory system, but cannot receive coherent requests, barriers, or distributed virtual memory messages.
Related information
10.10 External debug interface
AMBA AXI and ACE Protocol Specification
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