ARM Cortex-A72 MPCore Processor Technical Reference Manual : 7.7 External coherent interfaces

7.7 External coherent interfaces

The Cortex-A72 processor provides configurable options for either AMBA4 AXI Coherency Extensions (ACE) or CHI interconnect architectures.

Each interface option provides a 128-bit wide data interface to the system and supports 1:1 clock ratios with respect to the processor clock and N:1, integer multiple clock ratios, of the core clock.

Note

ACE is supported with the following restriction:

ARQOS and AWQOS signals are not present.

This section contains the following subsections:

7.7.1 L2 memory interface attributes.
7.7.2 Interface modes.
7.7.3 Snoop filter support.
7.7.4 Distributed virtual memory transactions.
7.7.5 External memory attributes.
7.7.6 ACE ARID and AWID assignment.
7.7.7 CHI LPID assignment.
7.7.8 ACE supported transfers.
7.7.9 CHI link layer flow control.
7.7.10 CHI DVM acceptance capability.
7.7.11 L2 Auxiliary Control Register settings.

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