7.7.1 L2 memory interface attributes

The following table shows the L2 memory interface attributes for the processor. The table lists the maximum possible values for the read and write issuing capabilities.

Table 7-4 L2 memory interface attributes

Attribute Value Description
Write issuing capability 16 16 outstanding writes supported that can be evictions, single writes, or write bursts of any memory type.
Read issuing capability 19, 23, or 27
If the core implements:
20-entry FEQ19 outstanding reads supported that can be line fills, single reads, or read bursts of any memory type.
24-entry FEQ23 outstanding reads supported that can be line fills, single reads, or read bursts of any memory type.
28-entry FEQ27 outstanding reads supported that can be line fills, single reads, or read bursts of any memory type.
Snoop acceptance capability 20 Up to 20 outstanding snoop requests are accepted on the AC channel in response to those requests on the CR channel.
DVM issuing capability 38, 46, or 54
If the processor implements:
20-entry FEQ38 DVM Message transactions supported (19 two-part messages)
24-entry FEQ46 DVM Message transactions supported (23 two-part messages)
28-entry FEQ54 DVM Message transactions supported (27 two-part messages)
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