ARM Cortex-A72 MPCore Processor Technical Reference Manual : 7.8.1 Transfer size support

ACP supports the following read-request transfer size and length combinations:

64-byte INCR request characterized by:
- ARLEN is 0x03, 4 beats.
- ARADDR aligned to 64-byte boundary, so ARADDR[5:0] is 0b00 0000.
- ARSIZE and ARBURST assume values of 0b100 and INCR respectively.
16-byte INCR request characterized by:
- ARLEN is 0x00, 1 beat.
- ARADDR aligned to 16-byte boundary, so ARADDR[3:0] is 0x0.

ACP supports the following write-request transfer size and length combinations:

64-byte INCR request characterized by:
- AWLEN is 0x03, 4 beats.
- AWADDR aligned to 64-byte boundary, so AWADDR[5:0] is 0b00 0000.
- AWSIZE and AWBURST assume values of 0b100 and INCR respectively.
- WSTRB for all beats must be the same and either all asserted or all deasserted.
16-byte INCR request characterized by:
- AWLEN is 0x00, 1 beat.
- AWADDR aligned to 16-byte boundary, so AWADDR[3:0] is 0x0.
- AWSIZE and AWBURST assume values of 0b100 and INCR respectively.
- WSTRB can take any value.

Requests not meeting these restrictions cause a SLVERR response on RRESP or BRESP.

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