3.2.3 Security state

An ARMv8 implementation that includes the EL3 Exception level provides the following Security states, each with an associated memory address space:
Secure state
In Secure state, the processor:
  • Can access both the Secure and the Non-secure memory address space.
  • When executing at EL3, can access all the system control resources.
Non-secure state
In Non-secure state, the processor:
  • Can access only the Non-secure memory address space.
  • Cannot access the Secure system control resources.
The AArch32 Security state model is unchanged from the model for an ARMv7-A architecture profile implementation that includes the Security Extensions and the Virtualization Extensions. When the implementation uses the AArch32 state for all Exception levels, many System registers are Banked to provide Secure and Non-secure instances, and:
  • The Secure instance is accessible only at EL3.
  • The Non-secure instance is accessible at EL1 or higher.
  • The two instances of a Banked register have the same name.
The 3.2.6 ARMv8 security model describes how the Security state interacts with other aspects of the ARMv8 architectural state.
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