3.4.1 Register summary

The following table gives a summary of the processor Jazelle registers that are accessed through the CP14 coprocessor in the AArch32 state. These registers are not implemented in the AArch64 state.

Table 3-3 Summary of Jazelle registers

CRn op1 CRm op2 Name Reset Description
c0 7 c0 0 JIDR 0x00000000 Jazelle Identity Register
c1 7 c0 0 JOSCR 0x00000000 Jazelle OS Control Register
c2 7 c0 0 JMCR 0x00000000 Jazelle Main Configuration Register
Related information
Jazelle Identity Register
Jazelle OS Control Register
Jazelle Main Configuration Register
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