ARM Cortex-A72 MPCore Processor Technical Reference Manual : 4.2.2 AArch64 exception handling registers

4.2.2 AArch64 exception handling registers

The following table shows the fault handling registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in the following table.

Table 4-2 AArch64 exception handling registers

Name	Type	Reset	Width	Description
AFSR0_EL1	RW	RES0	32	4.3.48 Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL1	RW	RES0	32	4.3.49 Auxiliary Fault Status Register 1, EL1 and EL3
ESR_EL1	RW	UNK	32	4.3.50 Exception Syndrome Register, EL1 and EL3
IFSR32_EL2	RW	UNK	32	4.3.51 Instruction Fault Status Register, EL2
AFSR0_EL2	RW	RES0	32	4.3.52 Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register
AFSR1_EL2	RW	RES0	32	4.3.53 Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register
ESR_EL2	RW	UNK	32	4.3.54 Exception Syndrome Register, EL2
AFSR0_EL3	RW	RES0	32	4.3.55 Physical Address Register, EL1
AFSR1_EL3	RW	RES0	32	4.3.49 Auxiliary Fault Status Register 1, EL1 and EL3
ESR_EL3	RW	UNK	32	4.3.50 Exception Syndrome Register, EL1 and EL3
FAR_EL1	RW	UNK	64	Fault Address Register, EL1
FAR_EL2	RW	UNK	64	Fault Address Register, EL2 ^a
HPFAR_EL2	RW	`0x00000000`	64	Hyp IPA Fault Address Register, EL2 ^a
FAR_EL3	RW	UNK	64	Fault Address Register, EL3 ^a
VBAR_EL1	RW	UNK	64	Vector Base Address Register, EL1 ^a
ISR_EL1	RO	UNK	32	Interrupt Status Register ^a
VBAR_EL2	RW	UNK	64	Vector Base Address Register, EL2 ^a

^a See the ARM^® Architecture Reference Manual ARMv8 for more information.

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