4.2.5 AArch64 cache maintenance operations

The following table shows the System instructions for cache and maintenance operations in AArch64 state. See the ARM® Architecture Reference Manual ARMv8 for more information about these operations.

Table 4-5 AArch64 cache maintenance operations

Name Description
IC IALLUIS
Instruction cache invalidate all to PoUa Inner Shareable
IC IALLU
Instruction cache invalidate all to PoU
IC IVAU
Instruction cache invalidate by virtual address (VA) to PoU
DC IVAC
Data cache invalidate by VA to PoCb
DC ISW
Data cache invalidate by set/way
DC CSW
Data cache clean by set/way
DC CISW
Data cache clean and invalidate by set/way
DC ZVA
Data cache zero by VA
DC CVAC
Data cache clean by VA to PoC
DC CVAU
Data cache clean by VA to PoU
DC CIVAC
Data cache clean and invalidate by VA to PoC
a PoU = Point of Unification. PoU is set by the BROADCASTINNER signal and can be in the L1 data cache or outside of the processor, in which case PoU is dependent on the external memory system.
b PoC = Point of Coherence. The PoC is always outside of the processor and is dependent on the external memory system.
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