4.2.9 AArch64 Performance Monitors registers

The following table shows the Performance Monitors registers in AArch64 state. Bits[63:32] are reset to 0x00000000 for all 64-bit registers in the following table.

Table 4-10 AArch64 Performance Monitors registers

Name Type Reset Width Description
PMCR_EL0 RW a 0x41023000 32 11.4.1 Performance Monitors Control Register, EL0
PMCNTENSET_EL0 RW UNK 32 Performance Monitors Count Enable Set Register 
PMCNTENCLR_EL0 RW UNK 32 Performance Monitors Enable Count Clear Register b
PMOVSCLR_EL0 RW UNK 32
Performance Monitors Overflow Flag Status Register b
PMSWINC_EL0 WO - 32
Performance Monitors Software Increment Register b
PMSELR_EL0 RW UNK 32
Performance Monitors Event Counter Selection Register b
PMCEID0_EL0 RO 0x7FFF0F3F 32 11.4.2 Performance Monitors Common Event Identification Register 0, EL0
PMCEID1_EL0 RO 0x00000000 32 Performance Monitors Common Event Identification Register 1 b
PMCCNTR_EL0 RW UNK 64
Performance Monitors Cycle Count Register b
PMXEVTYPER_EL0 RW UNK 32
Performance Monitors Selected Event Type Register b
PMCCFILTR_EL0 RW 0x00000000 32 Performance Monitors Cycle Count Filter Register b
PMXEVCNTR_EL0 RW UNK 32
Performance Monitors Selected Event Count Register b
PMUSERENR_EL0 RW 0x00000000 32
Performance Monitors User Enable Register b
PMINTENSET_EL1 RW UNK 32 Performance Monitors Interrupt Enable Set Register b
PMINTENCLR_EL1 RW UNK 32 Performance Monitors Interrupt Enable Clear Register b
PMOVSSET_EL0 RW UNK 32
Performance Monitors Overflow Flag Status Set Register b
a Access permissions also depend on the access condition. See 11.2.5 External register access permissions.
b See the ARM® Architecture Reference Manual ARMv8 for more information.
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