4.2.10 AArch64 reset registers

The following table shows the reset registers in AArch64 state.

Table 4-11 AArch64 reset registers

Name Type Reset Width Description
RVBAR_EL3 RO - a 64 4.3.60 Reset Vector Base Address, EL3
RMR_EL3 RW 0x00000000b 32 4.3.61 Reset Management Register, EL3
a The reset value depends on the RVBARADDR signal. Bits[63:32] are reset to 0x00000000.
b For a Cold reset, the AA64nAA32 signal sets the value of bit[0]. The following table assumes this signal is LOW.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.