4.2.11 Security registers

The following table shows the Security registers in AArch64 state.

Table 4-12 AArch64 security registers

Name Type Reset Width Description
SCR_EL3 RW 0x00000000 32 Secure Configuration Register, EL3 
SDER32_EL3 RW 0x00000000 32 Secure Debug Register, EL3 a
CPTR_EL3 RW 0x00000400 32 4.3.40 Architectural Feature Trap Register, EL3
MDCR_EL3 RW 0x00000000 32 Monitor Debug Configuration Register, EL3 a
AFSR0_EL3 RW RES0 32 4.3.48 Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL3 RW RES0 32 4.3.49 Auxiliary Fault Status Register 1, EL1 and EL3
VBAR_EL3 RW UNKb 64 Vector Base Address Register, EL3 a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
b The reset value of bits[63:32] is 0x00000000.
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