4.2.15 AArch64 IMPLEMENTATION DEFINED registers

The following table shows the IMPLEMENTATION DEFINED registers in AArch64 state. These registers provide test features and any required configuration options specific to the Cortex-A72 processor. If a register is not indicated as mapped to an AArch32 64-bit register, bits[63:32] are 0x00000000.

Table 4-15 AArch64 IMPLEMENTATION DEFINED registers

Name Type Reset Width Description
ACTLR_EL1 RW RES0 32 4.3.31 Auxiliary Control Register, EL1
ACTLR_EL2 RW 0x00000000 32 4.3.33 Auxiliary Control Register, EL2
ACTLR_EL3 RW 0x00000000 32 4.3.39 Auxiliary Control Register, EL3
AFSR0_EL1 RW RES0 32 4.3.48 Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL1 RW RES0 32 4.3.49 Auxiliary Fault Status Register 1, EL1 and EL3
AFSR0_EL2 RW RES0 32 4.3.52 Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register
AFSR1_EL2 RW RES0 32 4.3.53 Auxiliary Fault Status Register 1, EL2 and Hyp Auxiliary Instruction Fault Status Register
AFSR0_EL3 RW RES0 32 4.3.48 Auxiliary Fault Status Register 0, EL1 and EL3
AFSR1_EL3 RW RES0 32 4.3.49 Auxiliary Fault Status Register 1, EL1 and EL3
AMAIR_EL1 RW RES0 64 4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3
AMAIR_EL2 RW RES0 64 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2
AMAIR_EL3 RW RES0 64 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2
L2CTLR_EL1 RW 0x00000000a 32 4.3.58 L2 Control Register, EL1
L2ECTLR_EL1 RW 0x00000000 32 4.3.59 L2 Extended Control Register, EL1
IL1DATA0_EL1 RW UNK 32 4.3.62 Instruction L1 Data n Register, EL1
IL1DATA1_EL1 UNK
IL1DATA2_EL1 UNK
IL1DATA3_EL1 UNK
DL1DATA0_EL1 RW UNK 32 4.3.63 Data L1 Data n Register, EL1
DL1DATA1_EL1 UNK
DL1DATA2_EL1 UNK
DL1DATA3_EL1 UNK
DL1DATA4_EL1 UNK
RAMINDEX WO - 32 4.3.64 RAM Index operation
L2ACTLR_EL1 RW 0x0000000000000010b 32
CPUACTLR_EL1 RW 0x0000 0000 0000 0000 64 4.3.66 CPU Auxiliary Control Register, EL1
CPUECTLR_EL1c RW 0x0000 001B 0000 0000 64 4.3.67 CPU Extended Control Register, EL1
CPUMERRSR_EL1c RW UNK 64 4.3.68 CPU Memory Error Syndrome Register, EL1
L2MERRSR_EL1c RW UNKd 64 4.3.69 L2 Memory Error Syndrome Register, EL1
CBAR_EL1 RO UNKe 64 4.3.70 Configuration Base Address Register, EL1
a The reset value depends on the processor implementation and the state of the L2RSTDISABLE signal.
b This is the reset value for an ACE interface. For a CHI interface the reset value is 0x0000000000004018.
c Mapped to a 64-bit AArch32 register.
d Bits[47:40, 39:32, 31] are reset to zero.
e The reset value depends on the primary input, PERIPHBASE[43:18].
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