4.3.4 AArch32 Processor Feature Register 0, EL1

The ID_PFR0_EL1 characteristics are:

Provides information about the instruction sets supported by the processor in AArch32 state.
Usage constraints
The ID_PFR0_EL1 must be interpreted with the ID_PFR1_EL1.
The accessibility to the ID_PFR0_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
The ID_PFR0_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 ID_PFR0 register.
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the ID_PFR0_EL1 bit assignments.
Figure 4-4 ID_PFR0_EL1 bit assignments
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The following table shows the ID_PFR0_EL1 bit assignments.

Table 4-19 ID_PFR0_EL1 bit assignments

Bits Name Function
[31:16] - Reserved, RES0.
[15:12] State3
Indicates support for Thumb Execution Environment (ThumbEE) instruction set. This value is:
0x0Processor does not implement the ThumbEE instruction set.
[11:8] State2
Indicates support for Jazelle extension. This value is:
0x1Processor supports trivial implementation of Jazelle.
[7:4] State1
Indicates support for T32 instruction set. This value is:
0x3Processor supports T32 encoding after the introduction of Thumb-2 technology, and for all 16-bit and 32-bit T32 basic instructions.
[3:0] State0
Indicates support for A32 instruction set. This value is:
0x1Processor implements the A32 instruction set.
To access the ID_PFR0_EL1 in AArch64 state, read the register with:
MRS <Xt>, ID_PFR0_EL1; Read AArch32 Processor Feature Register 0
To access the ID_PFR0 in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c1, 0; Read AArch32 Processor Feature Register 0
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