The ID_PFR1_EL1 characteristics are:
- Provides information about the programmers model and extensions support
- Usage constraints
The ID_PFR1_EL1 must be interpreted with the
The accessibility to the ID_PFR1_EL1 by Exception level is:
||EL3(SCR.NS = 1)
||EL3(SCR.NS = 0)
The ID_PFR1_EL1 is:
- Common to Secure and Non-secure states.
- Architecturally mapped to the AArch32 ID_PFR1 register.
- See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the ID_PFR1_EL1 bit assignments.
Figure 4-5 ID_PFR1_EL1 bit assignments
The following table shows the ID_PFR1_EL1 bit assignments.
Table 4-20 ID_PFR1_EL1 bit assignments
Indicates support for the GIC
CP15 interface. The possible values are:
|No GIC CP15 registers are supported. This is the reset value
is tied HIGH.
|GICv3 CP15 registers are supported. This is the reset value
is tied LOW.
Indicates support for Generic
Timer Extension. This value is:
|Processor supports Generic Timer Extension.
Indicates support for
Virtualization Extensions. This value is:
|Processor supports Virtualization Extensions.
Indicates support for M-profile
programmers model. This value is:
|Processor does not support M-profile programmers model.
Indicates support for Security
Extensions. This value is:
|Processor supports Security Extensions. This includes
support for Monitor mode and the
Indicates support for the
standard programmers model for ARMv4 and later. This value is:
|Processor supports the standard programmers model for ARMv4
and later. The model supports User, FIQ, IRQ, Supervisor, Abort, Undefined,
and System modes.
To access the ID_PFR1_EL1 in AArch64 state, read the register with:
MRS <Xt>, ID_PFR1_EL1; Read AArch32 Processor Feature Register 1
To access the ID_PFR1 in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c1, 1; Read AArch32 Processor Feature Register 1