4.3.15 AArch32 Instruction Set Attribute Register 3, EL1

The ID_ISAR3_EL1 characteristics are:
Purpose
Provides information about the instruction set that the processor supports in AArch32.
Usage constraints
The ID_ISAR3 must be interpreted with:
  • ID_ISAR0_EL1.
  • ID_ISAR1_EL1.
  • ID_ISAR2_EL1.
  • ID_ISAR4_EL1.
  • ID_ISAR5_EL1.
The accessibility to the ID_ISAR3_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The ID_ISAR3_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 ID_ISAR3 register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the ID_ISAR3_EL1 bit assignments.
Figure 4-14 ID_ISAR3_EL1 bit assignments
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The following table shows the ID_ISAR3_EL1 bit assignments.

Table 4-29 ID_ISAR3_EL1 bit assignments

Bits Name Function
[31:28] ThumbEE Returns 0x0 to indicate no support for Thumb Execution Environment (ThumbEE) extension instructions.
[27:24] TrueNOP Returns 0x1 to indicate the processor implements true NOP instructions in both the A32 and T32 instruction sets, and additional NOP-compatible hints.
[23:20] ThumbCopy Returns 0x1 to indicate the processor supports T32 instruction set encoding T1 of the MOV (register) instruction, copying from a low register to a low register.
[19:16] TabBranch Returns 0x1 to indicate the processor implements the TBB and TBH table branch instructions in the T32 instruction set.
[15:12] SynchPrim
This field is used with the SynchPrim_frac field of ID_ISAR4 to indicate the supported Synchronization Primitive instructions. This value is:
0x2
Processor supports:
  • LDREX and STREX instructions.
  • CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.
  • LDREXD and STREXD instructions.
[11:8] SVC Returns 0x1 to indicate the processor implements the SVC instruction.
[7:4] SIMD
Returns 0x3 to indicate the processor implements the following Single Instruction Multiple Data (SIMD) instructions:
  • SSAT and USAT instructions, and the Q bit in the PSRs.
  • PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, UXTB16 instructions, and the GE[3:0] bits in the PSRs.
See the ARM® Architecture Reference Manual ARMv8 for more information.
[3:0] Saturate Returns 0x1 to indicate the processor implements the QADD, QDADD, QDSUB, QSUB saturate instructions and the Q bit in the PSRs.
To access the ID_ISAR3_EL1 in AArch64 state, read the register with:
MRS <Xt>, ID_ISAR3_EL1; Read AArch32 Instruction Set Attribute Register 3
To access the ID_ISAR3 in AArch32 state, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c2, 3; Read AArch32 Instruction Set Attribute Register 3
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