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ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
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4.3.21 AArch64 Memory Model Feature Register 0, EL1

The ID_AA64MMFR0_EL1 characteristics are:
Purpose
Provides information about the implemented memory model and memory management support in AArch64 state.
Usage constraints
The accessibility of the ID_AA64MMFR0_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
The external debug accessibility to the ID_AA64MMFR0[63:32] and the ID_AA64MMFR0[31:0] by condition code is:
Off DLK OSLK EDAD SLK Default
- - - - - RO
Table 10-1 External register access conditions describes the condition codes.
Configurations
The ID_AA64MMFR0_EL1 is architecturally mapped as follows:
  • [63:32] to external ID_AA64MMFR0[63:32] register.
  • [31:0] to external ID_AA64MMFR0[31:0] register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the ID_AA64MMFR0_EL1 bit assignments.
Figure 4-20 ID_AA64MMFR0_EL1 bit assignments
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The following table shows the ID_AA64MMFR0_EL1 bit assignments.

Table 4-35 ID_AA64MMFR0_EL1 bit assignments

Bits Name Function
[63:32] - Reserved, RES0.
[31:28] 4KB Returns 0x0 to indicate that the 4KB granule is supported.
[27:24] 64KB Returns 0x0 to indicate that the 64KB granule is supported.
[23:20] 16KB Returns 0x0 to indicate that the 16KB granule is not supported.
[19:16] - Reserved, RES0.
[15:12] SNSMem Returns 0x1 to indicate that the processor supports a distinction between Secure and Non-secure memory.
[11:8] BigEnd Returns 0x1 to indicate that the processor supports a mixed-endian configuration. The SCTLR_ELx.EE and SCTLR_EL1.E0E bits can be configured.
[7:4] ASIDBits Returns 0x2 to indicate that the processor supports 16 ASID bits.
[3:0] PARange Returns 0x4 to indicate that the processor supports a 44-bit physical address range, that is, 16TByte.
To access the ID_AA64MMFR0_EL1 in AArch64 state, read the register with:
MRS <Xt>, ID_AA64MMFR0_EL1; Read AArch64 Memory Model Feature Register 0
The ID_AA64MMFR0[31:0] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD38.
The ID_AA64MMFR0[63:32] can be accessed through the memory-mapped interface and the external debug interface, offset 0xD3C.
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