4.3.23 Cache Level ID Register, EL1

The CLIDR_EL1 characteristics are:
Purpose
Identifies:
  • The type of cache, or caches, implemented at each level, up to a maximum of seven levels
  • The Level of Coherency and Level of Unification for the cache hierarchy.
Usage constraints
The accessibility to the CLIDR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The CLIDR_EL1 is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch32 CLIDR register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the CLIDR_EL1 bit assignments.
Figure 4-22 CLIDR_EL1 bit assignments
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The following table shows the CLIDR_EL1 bit assignments.

Table 4-38 CLIDR_EL1 bit assignments

Bits Name Function
[31:30] - Reserved, RES0.
[29:27] LoUU
Indicates the Level of Unification Uniprocessor for the cache hierarchy. This value is:
0b001L1 cache is the last level of cache that must be cleaned or invalidated when cleaning or invalidating to the point of unification for the processor.
[26:24] LoC
Indicates the Level of Coherency for the cache hierarchy. This value is:
0b010L3 cache.
[23:21] LoUIS
Indicates the Level of Unification Inner Shareable for the cache hierarchy. This value is:
0b001L2 cache.
[20:18] Ctype7
Indicates the type of cache implemented at level 7. This value is:
0b000No cache.
[17:15] Ctype6
Indicates the type of cache implemented at level 6. This value is:
0b000No cache.
[14:12] Ctype5
Indicates the type of cache implemented at level 5. This value is:
0b000No cache.
[11:9] Ctype4
Indicates the type of cache implemented at level 4. This value is:
0b000No cache.
[8:6] Ctype3
Indicates the type of cache implemented at level 3. This value is:
0b000No cache.
[5:3] Ctype2
Indicates the type of cache implemented at level 2. This value is:
0b100Unified cache.
[2:0] Ctype1
Indicates the type of cache implemented at level 1. This value is:
0b011Separate instruction and data caches.
To access the CLIDR_EL1 in AArch64 state, read the register with:
MRS <Xt>, CLIDR_EL1; Read Cache Level ID Register
To access the CLIDR in AArch32 state, read the CP15 register with:
MRC p15, 1, <Rt>, c0, c0, 1; Read Cache Level ID Register
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