4.3.25 Cache Size Selection Register, EL1

The CSSELR_EL1 characteristics are:
Purpose
Selects the current CCSIDR_EL1, by specifying:
  • The required cache level.
  • The cache type, either instruction or data cache.
Usage constraints
The accessibility to the CSSELR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
If the CSSELR_EL1 level field is programmed to a cache level that is not implemented, then a read of CSSELR_EL1 returns an UNKNOWN value in CSSELR_EL1.Level.
Configurations
The CSSELR_EL1 is:
  • Banked for the Secure and Non-secure states.
  • Architecturally mapped to the Non-secure AArch32 CSSELR register.
Attributes
See the register summary in Table 4-1 AArch64 identification registers.
The following figure shows the CSSELR_EL1 bit assignments.
Figure 4-23 CSSELR_EL1 bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The following table shows the CSSELR_EL1 bit assignments.

Table 4-39 CSSELR_EL1 bit assignments

Bits Name Function
[31:4] - Reserved, RES0.
[3:1] Level
Cache level of required cache:
0b000Level 1.
0b001Level 2.
All other values are reserved.
[0] InD
Instruction not Data bit:
0Data or unified cache.
1Instruction cache.
To access the CSSELR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, CSSELR_EL1; Read Cache Size Selection Register
MSR CSSELR_EL1, <Xt>; Write Cache Size Selection Register
To access the CSSELR in AArch32 state, read or write the CP15 register with:
MRC p15, 2, <Rt>, c0, c0, 0; Read Cache Size Selection Register
MCR p15, 2, <Rt>, c0, c0, 0; Write Cache Size Selection Register
Related information
4.3.22 Cache Size ID Register, EL1
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.