4.3.38 System Control Register, EL3

The SCTLR_EL3 characteristics are:
Purpose
Provides top-level control of the system, including its memory system at EL3 in AArch64 state.
Usage constraints
The accessibility of the SCTLR_EL3 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - - RW RW
Configurations
The SCTLR_EL3 is:
  • A 32-bit register in AArch64 state.
  • Architecturally mapped to Secure AArch32 SCTLR register.
Attributes
See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the SCTLR_EL3 bit assignments.
Figure 4-34 SCTLR_EL3 bit assignments
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The following table shows the SCTLR_EL3 bit assignments.

Table 4-50 SCTLR_EL3 bit assignments

Bits Name Function
[63:30] - Reserved, RES0.
[29:28] - Reserved, RES1.
[27:26] - Reserved, RES0.
[25] EE
Exception endianness. The values are:
0Little-endian.
1Big-endian.
The reset value depends on the primary input CFGEND.
[24] - Reserved, RES0.
[23:22] - Reserved, RES1.
[21:20] - Reserved, RES0.
[19] WXN
Force treatment of all memory regions with write permissions as XN. The values are:
0Regions with write permissions are not forced to XN. This is the reset value.
1Regions with write permissions are forced to XN.
[18] - Reserved, RES1.
[17] - Reserved, RES0.
[16] - Reserved, RES1.
[15:13] - Reserved, RES0.
[12] I
Global instruction cache enable. The values are:
0Instruction caches disabled.
1Instruction caches enabled.
[11] -
Reserved, RES1.
[10:6] -
Reserved, RES0.
[5:4] -
Reserved, RES1.
[3] SA
Enables Stack Alignment check. The values are:
0Disables Stack Alignment check. This is the reset value
1Enables Stack Alignment check.
[2] C
Global enable for data and unified caches. The values are:
0Disables data and unified caches. This is the reset value.
1Enables data and unified caches.
[1] A
Enable Alignment fault check. The values are:
0Disables Alignment fault checking. This is the reset value.
1Enables Alignment fault checking.
[0] M
Global enable for the EL1 and EL0 stage 1 MMU. The values are:
0Disables EL1 and EL0 stage 1 MMU. This is the reset value.
1Enables EL1 and EL0 stage 1 MMU.
To access the SCTLR_EL3 in AArch64 state, read or write the register with:
MRS <Xt>, SCTLR_EL3; Read EL3 System Control Register
MSR SCTLR_EL3, <Xt>; Write EL3 System Control Register
Related information
4.5.5 System Control Register
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