4.3.44 Translation Table Base Register 0, EL1

The TTBR0_EL1 characteristics are:
Purpose
Holds the base address of translation table 0, and information about the memory it occupies. This is one of the translation tables for the stage 1 translation of memory accesses at EL1 if the highest Exception level is in AArch64 state.
Usage constraints
The TTBR0_EL1 is used in conjunction with TCR_EL1.
The accessibility to the TTBR0_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
TTBR0_EL1 is architecturally mapped to the Non-secure AArch32 register TTBR0.
Attributes
See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the TTBR0_EL1 bit assignments.
Figure 4-40 TTBR0_EL1 bit assignments
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The following table shows the TTBR0_EL1 bit assignments.

Table 4-56 TTBR0_EL1 bit assignments

Bits Name Function
[63:48] ASID
An ASID for the translation table base address.
The TCR_EL1.A1 field selects either the TTBR0.ASID or the TTBR1.ASID.
The TCR_EL1.AS bit selects whether all 16-bits [63:48] or the lower 8-bits [55:48] indicate the current ASID.
[47:10] BADDR Translation table base address. Defining the translation table base address width.
[9:0] - Reserved, RES0.
To access the TTBR0_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, TTBR0_EL1; Read EL1 Translation Table Base Register 0
MSR TTBR0_EL1, <Xt>; Write EL1 Translation Table Base Register 0
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