The TTBR0_EL3 characteristics are:
- Holds the base address of the translation table
for the stage 1 translation of memory accesses from EL3.
- Usage constraints
The accessibility to the TTBR0_EL3 by Exception
||EL3(SCR.NS = 1)
||EL3(SCR.NS = 0)
- TTBR0_EL3 is mapped to the Secure AArch32 TTBR0 register.
- See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the
TTBR0_EL3 bit assignments.
Figure 4-41 TTBR0_EL3 bit assignments
The following table shows the TTBR0_EL3
Table 4-57 TTBR0_EL3 bit assignments
||Translation table base address. Defining the translation table base address
To access the TTBR0_EL3 in AArch64 state, read or write the
MRS <Xt>, TTBR0_EL3; Read EL3 Translation Table Base Register 0
MSR TTBR0_EL3, <Xt>; Write EL3 Translation Table Base Register 0