4.3.47 Translation Control Register, EL3

The TCR_EL3 characteristics are:

Purpose
Controls translation table walks required for stage 1 translation of memory accesses from EL3 and holds cacheability and shareability information for the accesses.
Usage constraints
The accessibility of the TCR_EL3 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- - - - RW RW
Configurations
The TCR_EL3 is architecturally mapped to the Secure AArch32 TTBCR register.
Attributes
See the register summary in Table 4-3 AArch64 virtual memory control registers.
The following figure shows the TCR_EL3 bit assignments.
Figure 4-43 TCR_EL3 bit assignments
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The following table shows the TCR_EL3 bit assignments.

Table 4-59 TCR_EL3 bit assignments

Bits Name Function
[31] - Reserved, RES1.
[30:24] - Reserved, RES0.
[23] - Reserved, RES1.
[22:21] - Reserved, RES0.
[20] TBI
Top Byte Ignored. Indicates whether the top byte of the input address is used for address match. The values are:
0Top byte used in the address calculation.
1Top byte ignored in the address calculation.
[19] - Reserved, RES0.
[18:16] PS
Physical Address size. The possible values are:
0b00032 bits, 4GBytes.
0b00136 bits, 64GBytes.
0b01040 bits, 1TByte.
0b01142 bits, 4TBytes.
0b10044 bits, 16TBytes.
0b10148 bits, 256TBytes.
[15] - Reserved, RES0.
[14] TGO
TTBR0_EL3 granule size. The values are:
04KByte.
164KByte.
[13:12] SH0
Shareability attribute for memory associated with translation table walks using TTBR0. The values are:
0b00Non-shareable.
0b01Reserved.
0b10Outer Shareable.
0b11Inner Shareable.
[11:10] ORGN0
Outer cacheability attribute for memory associated with translation table walks using TTBR0. The values are:
0b00Normal memory, Outer Non-cacheable.
0b01Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10Normal memory, Outer Write-Through Cacheable.
0b11Normal memory, Outer Write-Back no Write-Allocate Cacheable.
[9:8] IRGN0
Inner cacheability attribute for memory associated with translation table walks using TTBR0. The values are:
0b00Normal memory, Inner Non-cacheable.
0b01Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10Normal memory, Inner Write-Through Cacheable.
0b11Normal memory, Inner Write-Back no Write-Allocate Cacheable.
[7:6] - Reserved, RES0.
[5:0] T0SZ Size offset of the memory region addressed by TTBR0. The region size is 2(64–TSIZE) bytes.
To access the TCR_EL3 in AArch64 state, read or write the register with:
MRS <Xt>, TCR_EL3; Read EL3 Translation Control Register
MRS TCR_EL3, <Xt>; Read EL3 Translation Control Register
Related information
4.5.15 Translation Table Base Control Register
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