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Home > System Control > AArch64 register descriptions > Physical Address Register, EL1 |
EL0 | EL1(NS) | EL1(S) | EL2 | EL3(SCR.NS = 1) | EL3(SCR.NS = 0) |
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- | RW | RW | RW | RW | RW |
Table 4-67 PAR_EL1 pass bit assignments
Bits | Name | Function | ||||||||||||||||||||
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[63:60] | AttrH | Defines Device memory or Normal
memory plus Outer cacheability. Must be used in conjunction with AttrL. The
possible values are:
All other values are reserved.
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[59:56] | AttrL | Defines Device memory or Normal
memory plus Inner cacheability. Must be interpreted in conjunction with AttrH. The
possible values are:
All other values are reserved.
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[55:44] | - | Reserved, RES0. | ||||||||||||||||||||
[43:12] | PA | Physical address. The Physical Address corresponding to the supplied Virtual Address. Returns address bits[31:12]. | ||||||||||||||||||||
[11] | - | Reserved, RES1. | ||||||||||||||||||||
[10] | - | Reserved, RES0. | ||||||||||||||||||||
[9] | NS | Non-secure. The NS attribute
for a translation table entry read from Secure state.
This
bit is UNKNOWN for a
translation table entry from Non-secure state.
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[8:7] | SHA | Shareability attribute for the
Physical Address returned from a translation table entry. The values are:
NoteThe SHA bit takes the value of0b10 for:
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[6:1] | - | Reserved, RES0. | ||||||||||||||||||||
[0] | F | Pass/Fail bit. Indicates
whether the conversion completed successfully. This value is:
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Table 4-68 PAR_EL1 fail bit assignments
Bits | Name | Function | ||||
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[63:12] | - | Reserved, RES0. | ||||
[11] | - | Reserved, RES1. | ||||
[10] | - | Reserved, RES0. | ||||
[9] | S | Stage of fault. Indicates the
state where the translation aborted. The values are:
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[8] | PTW | Indicates a stage 2 fault
during a stage 1 table walk. The values are:
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[7] | - | Reserved, RES0. | ||||
[6:1] | FST | Fault status code, as shown in
the Data Abort ESR encoding. See the ARM® Architecture Reference Manual ARMv8 for more
information.
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[0] | F | Pass/Fail bit. Indicates
whether the conversion completed successfully. The value is:
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MRS <Xt>, PAR_EL1; Read EL1 Physical Address Register MSR PAR_EL1, <Xt>; Write EL1 Physical Address Register