The RVBAR_EL3 characteristics are:
Defines the address that execution starts from after
reset when executing in the AArch64 state.
RVBAR_EL3 is part of the reset management registers functional
- Usage constraints
The accessibility of the RVBAR_EL3 by Exception
||EL3(SCR.NS = 1)
||EL3(SCR.NS = 0)
Only implemented if the highest Exception level
implemented is EL3.
- See the register summary in Table 4-11 AArch64 reset registers.
The following figure shows the
RVBAR_EL3 bit assignments.
Figure 4-52 RVBAR_EL3 bit assignments
The following table shows the RVBAR_EL3
Table 4-71 RVBAR_EL3 bit assignments
||Reset Vector Base Address
||Reset Vector Base Address when executing in the AArch64 state. The reset address
n is set by the RVBARADDRn[43:2] input signals.
To access the RVBAR_EL3 in AArch64 state, read the register
MRS <Xt>, RVBAR_EL3; Read RVBAR_EL3 Reset Vector Base Address Register