4.3.66 CPU Auxiliary Control Register, EL1

The CPUACTLR_EL1 characteristics are:
Purpose
Provides IMPLEMENTATION DEFINED configuration and control options for the processor. There is one 64-bit CPU Auxiliary Control Register for each core in the cluster.
Usage constraints
The accessibility to the CPUACTLR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RWa RWb RW RW
The CPU Auxiliary Control Register can only be written when the system is idle. ARM recommends that you write to this register after a powerup reset, before the MMU is enabled, and before any ACE or ACP traffic begins.

Note

Setting many of these bits can cause significantly lower performance on your code. Therefore, it is suggested that you do not modify this register unless directed by ARM.
Configurations
CPUACTLR_EL1 is:
  • Common to the Secure and Non-secure states.
  • A 64-bit read/write register.
  • Architecturally mapped to the AArch32 CPUACTLR register.
Attributes
See the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the CPUACTLR_EL1[63:32] bit assignments.
Figure 4-73 CPUACTLR_EL1[63:32] bit assignments
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The following table shows the CPUACTLR_EL1[63:32] bit assignments.

Table 4-77 CPUACTLR_EL1[63:32] bit assignments

Bits Name Function
[63]c Force processor memory-system RCG enables active
Forces processor memory-system RCG enables active:
0
Enables the processor memory-system RCGs for additional clock gating and potentially reduce dynamic power dissipation. This is the reset value.
1
Forces the processor memory-system RCG enables HIGH.
Setting this bit to 1 has no effect if the processor is configured to not include RCGs. See Regional clock gating.
[62]c Force processor non-memory-system RCG enables active
Forces processor non-memory-system RCG enables active:
0
Enables the processor non-memory-system RCGs for additional clock gating and potentially reduce dynamic power dissipation. This is the reset value.
1
Forces the processor non-memory-system RCG enables HIGH.
Setting this bit to 1 has no effect if the processor is configured to not include RCGs. See Regional clock gating.
[61]c Force processor Decode and Integer Execute idle RCG enables active
Forces processor Decode and Integer Execute idle RCG enables active:
0
Enables the processor Decode and Integer Execute idle RCGs for additional clock gating and potentially reduce dynamic power dissipation. This is the reset value.
1
Forces the processor Decode and Integer Execute idle RCG enables HIGH.
Setting this bit to 1 has no effect if the processor is configured to not include RCGs. See Regional clock gating.
[60]c Force processor Dispatch idle RCG enables active
Forces processor Dispatch idle RCG enables active:
0
Enables the processor Dispatch idle RCGs for additional clock gating and potentially reduce dynamic power dissipation. This is the reset value.
1
Forces the processor Dispatch idle RCG enables HIGH.
Setting this bit to 1 has no effect if the processor is configured to not include RCGs. See Regional clock gating.
[59]c Disable load pass DMB
Disables load pass DMB. This does not include the implicit barrier from Load-Acquire and Load-Acquire Exclusive. The possible values are:
0
Enables load pass DMB. This is the reset value.
1
Disables load pass DMB.
[58]c Disable DMB nullification
Disables DMB nullification. This includes the implicit barrier from Store-Release and Store-Release Exclusive:
0
Enables DMB nullification. This is the reset value.
1
Disables DMB nullification.
[57]c
Treat DMB st/st and DMB ld/all as DMB all/all.
Treat DSB st/st and DSB ld/all as DSB all/all.
Treats DMB st/st and DMB ld/all as DMB all/all. Treat DSB st/st and DSB ld/all as DSB all/all. This does not include the implicit barrier from Load-Acquire/Store-Release. The possible values are:
0
Normal behavior. This the reset value.
1
  • Treat DMB st/st and DMB ld/all as DMB all/all.
  • Treat DSB st/st and DSB ld/all as DSB all/all.
[56]c Disable Load–store hardware prefetcher
Disables Load–store hardware prefetcher:
0
Enables Load–store hardware prefetcher. This the reset value.
1
Disables Load–store hardware prefetcher.
[55]c Disable load pass store
Disables load pass store:
0
Enables load pass store. This the reset value.
1
Disables load pass store.
[54]c Treat GRE/nGRE as nGnRE
Treat GRE and nGRE as nGnRE:
0
Enables optimization for GRE and nGRE load/store. This is the reset value.
1
Treats GRE and nGRE as nGnRE. Disables optimization for GRE and nGRE load/store.
[53]c Treat DMB and DSB as if their domain field is SY
Treats DMB and DSB as if their domain field is SY. The possible values are:
0
Normal behavior. This is the reset value.
1
Treat DMB NSH, DMB ISH, and DMB OSH as DMB SY.
Treat DSB NSH, DSB ISH, and DSB OSH as DSB SY.
[52]c Disable over-read from LDNP instruction
Disables over-read from LDNP instruction:
0
Enables the over-read from LDNP instruction. This is the reset value.
1
Disables the over-read from LDNP instruction.
[51]c Enable contention detection and fast exclusive monitor path
Enables contention detection and fast exclusive monitor path:
0
Disables contention detection and fast exclusive monitor path. This is the reset value.
1
Enables contention detection and fast exclusive monitor path.
[50]c Disable store streaming on NC/GRE memory type
Disables store streaming on NC/GRE memory type:
0
Enables store streaming on NC/GRE memory type. This is the reset value.
1
Disables store streaming on NC/GRE memory type.
[49]c Disable non-allocate hint of Write-Back No-Allocate (WBNA) memory type
Disables non-allocate hint of Write-Back No-Allocate memory type:
0
Enables non-allocate hint of WBNA memory type. This is the reset value.
1
Disables non-allocate hint of WBNA memory type.
[48]c Disable early speculative read access from LS to L2
Disables early speculative read access from LS to L2:
0
Enables speculative early read access from LS to L2. This is the reset value.
1
Disables speculative early read access from LS to L2.
[47]c Disable D-side L1/L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger.
Disables L1 and L2 hardware prefetch across 4KB page boundary even if page is 64KB or larger:
0
Enables D-side L1/L2 hardware prefetch across 4KB page boundary if the page is 64KB or larger. This is the reset value.
1
Disables D-sideL1/L2 hardware prefetch across 4KB page boundary even if the page is 64KB or larger.
[46]c Disable multiple outstanding L1 Data TLB misses and L2 TLB hit under miss
Disables multiple outstanding L1 Data TLB misses and L2 TLB hit under miss:
0
Enables multiple outstanding L1 Data TLB misses and L2 TLB hit under miss. This is the reset value.
1
Disables multiple outstanding L1 Data TLB misses and L2 TLB hit under miss.
[45]c Disable L1-DCache way tracker
Disables L1-DCache way tracker:
0
Enables L1-DCache way tracker. This is the reset value.
1
Disables L1-DCache way tracker.
[44]c Enable data cache clean as data cache clean/invalidate
Enables data cache clean as data cache clean and invalidate:
0
Normal behavior, executes data cache clean as data cache clean.
This is the reset value.
1
Executes data cache clean as data cache clean and invalidate.
[43]c Disable VA based hardware prefetch
Disables the Load/Store hardware prefetcher from using VA to cross page boundaries:
0
Enables the Load/Store hardware prefetcher to use VA in generating prefetches that can cross page boundaries. This is the reset value.
1
Disables the Load/Store hardware prefetcher from using VA in prefetch generation.
[42]c Disable prefetch requests from ReadUnique transactions
Disables prefetch requests from ReadUnique transactions:
0
Enables prefetch requests to be generated by ReadUnique transactions. This is the reset value.
1
Disables prefetch requests to be generated by ReadUnique transactions.
[41]c Enable snoop hazard while waiting for second half of atomic exclusive pair
Enables snoop hazard while waiting for second half of atomic exclusive pair:
0
Disable snoop hazard while waiting for second half of atomic exclusive pair. This is the reset value.
1
Enable snoop hazard while waiting for second half of the atomic exclusive pair.
[40] - Reserved, RES0.
[39]c Disable instruction merging
Disables instruction merging:
0
Enables instruction merging. This is the reset value.
1
Disables instruction merging.
[38]c Force FPSCR write flush
Forces FPSCR write flush:
0
Normal behavior for FPSCR writes. This is the reset value.
1
Forces synchronizing flush on all FPSCR writes.
[37]c Disable instruction group split
Disables instruction group split:
0
Enables instruction group split. This is the reset value.
1
Disables instruction group split.
[36]c Force implicit DSB on an ISB event
Forces implicit DSB on ISB event:
0
Normal behavior. This is the reset value.
1
Force implicit DSB on an ISB event.
[35]c Disable ISB optimization
Disables ISB optimization:
0
Enables ISB optimization. This is the reset value.
1
Disables ISB optimization.
[34]c Disable Static Branch Predictor
Disables static branch predictor:
0
Enables static branch predictor. This is the reset value.
1
Disables static branch predictor.
[33]c Disable main prediction suppression at target fetch of microBTB
Disables main prediction suppression at target fetch of microBTB:
0
Enables prediction suppression at target fetch of microBTB. This is the reset value.
1
Disables prediction suppression at target fetch of microBTB.
[32]c Disable L1 Instruction Cache prefetch
Disables L1 Instruction Cache prefetch:
0
Enables Instruction Cache prefetch. This is the reset value.
1
Disables Instruction Cache prefetch.
The following figure shows the CPUACTLR_EL1[31:0] bit assignments.
Figure 4-74 CPUACTLR_EL1[31:0] bit assignments
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The following table shows the CPUACTLR_EL1[31:0] bit assignments.

Table 4-78 CPUACTLR_EL1[31:0] bit assignments

Bits Name Function
[31] Snoop-delayed exclusive handling
Snoop-delayed exclusive handling. The possible values are:
0Normal exclusive handling behavior. This is the reset value.
1Modifies exclusive handling behavior by delaying certain snoop requests.
[30]d Force main clock enable active
Forces main clock enable active. The possible values are:
0Does not prevent the clock generator from stopping the processor clock. This is the reset value.
1Prevents the clock generator from stopping the processor clock.
If the processor dynamic retention feature is used then this bit must be zero. See Processor dynamic retention.
[29]d Force Advanced SIMD and floating-point clock enable active
Forces Advanced SIMD and Floating-point clock enable active. The possible values are:
0Does not prevent the clock generator from stopping the Advanced SIMD and Floating-point clock. This is the reset value.
1Prevents the clock generator from stopping the Advanced SIMD and Floating-point clock.
If the processor dynamic retention feature is used then this bit must be zero. See Processor dynamic retention.
[28:27] Write streaming no-allocate threshold
Write streaming no-allocate threshold. The possible values are:
0b0012th consecutive streaming cache line does not allocate in the L1 or L2 cache. This is the reset value.
0b01128th consecutive streaming cache line does not allocate in the L1 or L2 cache.
0b10512th consecutive streaming cache line does not allocate in the L1 or L2 cache.
0b11Disables streaming. All Write-Allocate lines allocate in the L1 or L2 cache.
[26:25] Write streaming no-L1-allocate threshold
Write streaming no-L1-allocate threshold. The possible values are:
0b004th consecutive streaming cache line does not allocate in the L1 cache. This is the reset value.
0b0164th consecutive streaming cache line does not allocate in the L1 cache.
0b10128th consecutive streaming cache line does not allocate in the L1 cache.
0b11Disables streaming. All Write-Allocate lines allocate in the L1 cache.
[24] Non-cacheable streaming enhancement
Non-cacheable streaming enhancement. You can set this bit only if your memory system meets the requirement that cache line fill requests from the Cortex-A72 processor are atomic. The possible values are:
0Disables higher performance Non-cacheable load forwarding. This is the reset value.
1Enables higher performance Non-cacheable load forwarding. See 6.4.4 Non-cacheable streaming enhancement for more information.
[23]d Force in-order requests to the same set and way
Forces in-order requests to the same set and way. The possible values are:
0Does not force in-order requests to the same set and way. This is the reset value.
1Forces in-order requests to the same set and way.
[22]d Force in-order load issue
Forces in-order load issue. The possible values are:
0Does not force in-order load issue. This is the reset value.
1Forces in-order load issue.
[21]d Disable L2 TLB prefetching
Disables L2 TLB prefetching. The possible values are:
0Enables L2 TLB prefetching. This is the reset value.
1Disables L2 TLB prefetching.
[20]d Disable L2 translation table walk IPA PA cache
Disables L2 translation table walk Immediate Physical Address (IPA) to Physical Address (PA) cache. The possible values are:
0Enables L2 translation table walk IPA to PA cache. This is the reset value.
1Disables L2 translation table walk IPA to PA cache.
[19]d Disable L2 stage 1 translation table walk cache
Disables L2 stage 1 translation table walk cache. The possible values are:
0Enables L2 stage 1 translation table walk cache. This is the reset value.
1Disables L2 stage 1 translation table walk cache.
[18]d Disable L2 stage 1 translation table walk L2 PA cache
Disables L2 stage 1 translation table walk L2 PA cache. The possible values are:
0Enables L2 stage 1 translation table walk L2 PA cache. This is the reset value.
1Disables L2 stage 1 translation table walk L2 PA cache.
[17]d Disable L2 TLB performance optimization
Disables L2 TLB performance optimization. The possible values are
0Enables L2 TLB optimization. This is the reset value.
1Disables L2 TLB optimization.
[16]d Enable full Strongly-ordered and Device load replay
Enables full Strongly-ordered or Device load replay. The possible values are:
0Disables full Strongly-ordered or Device load replay. This is the reset value.
1Enables full Strongly-ordered or Device load replay.
[15]d Force in-order issue in branch execute unit
Forces in-order issue in branch execute unit. The possible values are:
0Disables forced in-order issue. This is the reset value.
1Forces in-order issue.
[14]d Force limit of one instruction group commit/de-allocate per cycle
Forces limit of one instruction group to commit and de-allocate per cycle. The possible values are:
0Normal commit and de-allocate behavior. This is the reset value.
1Limits commit and de-allocate to one instruction group per cycle.
[13]d Flush after Special Purpose Register (SPR) writes
Flushes after certain SPR writes. The possible values are:
0Normal behavior for SPR writes. This is the reset value.
1Flushes after certain SPR writes.
[12]d Force push of SPRs
Forces push of certain SPRs from local dispatch copies to shadow copies. The possible values are:
0Normal behavior for SPRs. This is the reset value.
1Pushes certain SPRs from local dispatch copies to shadow copies.

Note

Setting this bit to 1 forces the processor to behave as if bit[13] is set to 1.
[11]d Limit to one instruction per instruction group
Limits to one instruction per instruction group. The possible values are:
0Normal instruction grouping. This is the reset value.
1Limits to one instruction per instruction group.
[10]d Force serialization after each instruction group
Forces serialization after each instruction group. The possible values are:
0Disables forced serialization after each instruction group. This is the reset value.
1Forces serialization after each instruction group.

Note

Setting this bit to 1 forces the processor to behave as if bit[11] is set to 1.
[9]d Disable flag renaming optimization
Disables flag renaming optimization. The possible values are:
0Enables normal flag renaming optimization. This is the reset value.
1Disables normal flag renaming optimization.
[8]d Execute WFI instruction as a NOP instruction
Executes WFI instruction as a NOP instruction. The possible values are:
0Executes WFI instruction as defined in the ARM® Architecture Reference Manual ARMv8. This is the reset value.
1Executes WFI instruction as a NOP instruction, and does not put the processor in WFI low-power state.
[7]d Execute WFE instruction as a NOP instruction
Executes WFE instruction as a NOP instruction. The possible values are:
0Executes WFE instruction as defined in the ARM® Architecture Reference Manual ARMv8. This is the reset value.
1Executes WFE instruction as a NOP instruction, and does not put the processor in WFE low-power state.
[6] - Reserved, RES0.
[5]d Execute PLD and PLDW instructions as a NOP
Executes PLD and PLDW instructions as a NOP instruction. The possible values are:
0Executes PLD and PLDW instructions as defined in the ARM® Architecture Reference Manual ARMv8. This is the reset value.
1Executes PLD and PLDW instructions as a NOP instruction.
[4]d Disable indirect predictor
Disables indirect predictor. The possible values are:
0Enables indirect predictor. This is the reset value.
1Disables indirect predictor.
[3]d Disable micro-BTB
Disables micro-Branch Target Buffer (BTB). The possible values are:
0Enables micro-BTB. This is the reset value.
1Disables micro-BTB.
[2] - Reserved, RES0.
[1]d Disable Instruction Cache miss streaming
Disables Instruction Cache miss streaming. The possible values are:
0Enables Instruction Cache miss streaming. Sequential fetches resulting from Instruction Cache misses wait until individual packets arrive. This is the reset value.
1Disables Instruction Cache miss streaming. Sequential fetches resulting from Instruction Cache misses internally generate misses for each packet.
[0]d
Enable invalidates of BTB
Enables invalidate of BTB. The possible values are:
0The Invalidate Instruction Cache All and Invalidate Instruction Cache by VA instructions only invalidates the instruction cache array. This is the reset value.
1The Invalidate Instruction Cache All and Invalidate Instruction Cache by VA instructions invalidates the instruction cache array and branch target buffer.
To access the CPUACTLR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, S3_1_c15_c2_0; Read EL1 CPU Auxiliary Control Register
MSR S3_1_c15_c2_0, <Xt>; Write EL1 CPU Auxiliary Control Register
To access the CPUACTLR in AArch32 state, read or write the CP15 register with:
MRRC p15, 0, <Rt>, <Rt2>, c15; Read CPU Auxiliary Control Register
MCRR p15, 0, <Rt>, <Rt2>, c15; Write CPU Auxiliary Control Register
a Write access if ACTLR_EL3.CPUACTLR is 1 and ACTLR_EL2.CPUACTLR is 1, or ACTLR_EL3.CPUACTLR is 1 and SCR.NS is 0.
b Write access if ACTLR_EL3.CPUACTLR is 1.
c This bit is used internally for debugging and characterization purposes only. For normal operation, ARM recommends that you do not change the value of this bit from its reset value.
d This bit is used internally for debugging and characterization purposes only. For normal operation, ARM recommends that you do not change the value of this bit from its reset value.
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