4.3.69 L2 Memory Error Syndrome Register, EL1

The L2MERRSR_EL1 characteristics are:

Purpose
Holds the number of memory errors that have occurred in the following L2 RAMs:
  • L2 Tag RAM.
  • L2 Data RAM.
  • L2 Snoop Tag RAM.
  • L2 Dirty RAM.
  • L2 Inclusion PLRU RAM.
A write of any value to the register updates the register to zero.
Usage constraints
The accessibility to the L2MERRSR_EL1 by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The L2MERRSR_EL1 is:
  • Common to the Secure and Non-secure states.
  • A 64-bit read/write register.
  • Architecturally mapped to the AArch32 L2MERRSR register.
AttributesSee the register summary in Table 4-15 AArch64 IMPLEMENTATION DEFINED registers.
The following figure shows the L2MERRSR_EL1 bit assignments.
Figure 4-77 L2MERRSR_EL1 bit assignments
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The following table shows the L2MERRSR_EL1 bit assignments.

Table 4-81 L2MERRSR_EL1 bit assignments

Bits Name Function
[63] Fatal Fatal bit. This bit is set to 1 on the first memory error that caused a Data Abort. It is a sticky bit so that after it is set, it remains set until the register is written. The reset value is 0.
[62:48] - Reserved, RES0.
[47:40]
Other error count
This field is set to 0 on the first memory error and is incremented on any memory error that does not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set. The reset value is 0.
[39:32] Repeat error count This field is set to 0 on the first memory error and is incremented on any memory error that exactly matches the RAMID, bank, way or index information in this register while the sticky Valid bit is set. The reset value is 0.
[31] Valid Valid bit. This bit is set to 1 on the first memory error. It is a sticky bit so that after it is set, it remains set until the register is written. The reset value is 0.
[30:24] RAMID
RAM Identifier. Indicates the RAM where the first memory error occurred. The possible values are:
0b001 0000L2 Tag RAM.
0b001 0001L2 Data RAM.
0b001 0010L2 Snoop Tag RAM.
0b001 0100L2 Dirty RAM.
0b0011000L2 Inclusion PLRU RAM.
[23:22] - Reserved, RES0.
[21:18] CPUID/Way
Indicates which processor and way of the RAM where the first memory error occurred.
For L2 Tag, Data, and Dirty RAMs, bits[21:18] indicate one of 16 ways, from way 0 to way 15.
For L2 Snoop Tag RAM:
  • Bits[20:19] indicate which processor of the L1 Tag RAM.
  • Bit[18] indicates which way of the Tag RAM.
The possible values are:
0b0000CPU0 tag, way 0.
0b0001CPU0 tag, way 1.
0b0010CPU1 tag, way 0.
0b0011CPU1 tag, way 1.
0b0100CPU2 tag, way 0.
0b0101CPU2 tag, way 1.
0b0110CPU3 tag, way 0.
0b0111CPU3 tag, way 1.
[17:0] Index Indicates the index address of the first memory error.

Note

  • If two or more memory errors in the same RAM occur in the same cycle, only one error is reported.
  • If two or more first memory error events from different RAMs occur in the same cycle, one of the errors is selected arbitrarily, while the Other error count field is only incremented by one.
  • If two or more memory error events from different RAMs, that do not match the RAMID, bank, way, or index information in this register while the sticky Valid bit is set, occur in the same cycle, the Other error count field is only incremented by one.
To access the L2MERRSR_EL1 in AArch64 state, read or write the register with:
MRS <Xt>, S3_1_c15_c2_3 ; Read EL1 L2 Memory Error Syndrome Register
MSR S3_1_c15_c2_3, <Xt> ; Write EL1 L2 Memory Error Syndrome Register
To access the L2MERRSR in AArch32 state, read or write the CP15 register with:
MRRC p15, 3, <Rt>, <Rt2>, c15; Read L2 Memory Error Syndrome Register
MCRR p15, 3, <Rt>, <Rt2>, c15; Write L2 Memory Error Syndrome Register
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