4.4.1 c0 registers

The following table shows the CP15 System registers when CRn is c0 and the processor is in AArch32 state.

Table 4-84 c0 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 MIDR RO 0x410FD081 Main ID Register. See 4.3.1 Main ID Register, EL1.
    1 CTR RO 0x8444C004 Cache Type Register. See 4.3.26 Cache Type Register, EL0.
    2 TCMTR - 0x00000000 4.5.1 TCM Type Register.
    3 TLBTR RO 0x00000000 4.5.2 TLB Type Register.
    4, 7 MIDR RO 0x410FD081 Aliases of Main ID Register, see 4.3.1 Main ID Register, EL1.
    5 MPIDR RO 0x80000003a 4.5.3 Multiprocessor Affinity Register.
    6 REVIDR RO 0x00000000 Revision ID Register. See 4.3.3 Revision ID Register, EL1.
  c1 0 ID_PFR0 RO 0x00000131 Processor Feature Register 0. See 4.3.4 AArch32 Processor Feature Register 0, EL1.
    1 ID_PFR1 RO 0x00011011b Processor Feature Register 1. See 4.3.5 AArch32 Processor Feature Register 1, EL1.
    2 ID_DFR0 RO 0x03010066 Debug Feature Register 0. See 4.3.6 AArch32 Debug Feature Register 0, EL1.
    3 ID_AFR0 RO 0x00000000 Auxiliary Feature Register 0. See 4.3.7 AArch32 Auxiliary Feature Register 0, EL1.
    4 ID_MMFR0 RO 0x10201105 Memory Model Feature Register 0. See 4.3.8 AArch32 Memory Model Feature Register 0, EL1.
    5 ID_MMFR1 RO 0x40000000 Memory Model Feature Register 1. See 4.3.9 AArch32 Memory Model Feature Register 1, EL1.
    6 ID_MMFR2 RO 0x01260000 Memory Model Feature Register 2. See 4.3.10 AArch32 Memory Model Feature Register 2, EL1.
    7 ID_MMFR3 RO 0x02102211 Memory Model Feature Register 3. See 4.3.11 AArch32 Memory Model Feature Register 3, EL1.
  c2 0 ID_ISAR0 RO 0x02101110 Instruction Set Attribute Register 0. See 4.3.12 AArch32 Instruction Set Attribute Register 0, EL1.
    1 ID_ISAR1 RO 0x13112111 Instruction Set Attribute Register 1. See 4.3.13 AArch32 Instruction Set Attribute Register 1, EL1.
    2 ID_ISAR2 RO 0x21232042 Instruction Set Attribute Register 2. See 4.3.14 AArch32 Instruction Set Attribute Register 2, EL1.
    3 ID_ISAR3 RO 0x01112131 Instruction Set Attribute Register 3. See 4.3.15 AArch32 Instruction Set Attribute Register 3, EL1.
    4 ID_ISAR4 RO 0x00011142 Instruction Set Attribute Register 4. See 4.3.16 AArch32 Instruction Set Attribute Register 4, EL1.
    5 ID_ISAR5 RO 0x00010001c Instruction Set Attribute Register 5. See 4.3.17 AArch32 Instruction Set Attribute Register 5, EL1.
1 c0 0 CCSIDR RO UNK Cache Size ID Register. See 4.3.22 Cache Size ID Register, EL1.
    1 CLIDR RO 0x0A200023 Cache Level ID Register. See 4.3.23 Cache Level ID Register, EL1.
    7 AIDR - 0x00000000 Auxiliary ID Register. See 4.3.24 Auxiliary ID Register, EL1.
2 c0 0 CSSELR RW UNK Cache Size Selection Register. See 4.3.25 Cache Size Selection Register, EL1.
4 c0 0 VPIDR RW -d Virtualization Processor ID Register. See 4.3.28 Virtualization Processor ID Register, EL2.
    5 VMPIDR RO -e Virtualization Multiprocessor ID Register. See 4.5.4 Virtualization Multiprocessor ID Register.
a The reset value depends on the primary inputs, CLUSTERIDAFF1 and CLUSTERIDAFF2, and the number of cores that the device implements. The value shown is for a four processor implementation, with CLUSTERIDAFF1 and CLUSTERIDAFF2 set to zero.
b The reset value depends on the primary input GICCDISABLE. The value shown assumes the GICCDISABLE signal is tied HIGH.
c The reset value is 0x00011121 if the Cryptography engine is implemented.
d The reset value is the value of the Main ID Register.
e The reset value is the value of the Multiprocessor Affinity Register.
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