4.4.2 c1 registers

The following table shows the System registers when CRn is c1 and the processor is in AArch32 state.

Table 4-85 c1 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 SCTLR RW 0x00C50838a 4.5.5 System Control Register.
  1 ACTLR - 0x00000000 Auxiliary Control Register. See 4.3.39 Auxiliary Control Register, EL3.
  2 CPACR RW 0x00000000 4.5.6 Architectural Feature Access Control Register.
  c1 0 SCR RW 0x00000000 4.5.7 Secure Configuration Register.
  1 SDER RW 0x00000000 Secure Debug Enable Register. 
  2 NSACR RW c 0x00000000 4.5.8 Non-secure Access Control Register.
  c3 1 SDCR RW 0x00000000 4.5.9 Secure Debug Configuration Register.
4 c0 0 HSCTLR RW 0x30C50838 Hyp System Control Register. b
  1 HACTLR RW 0x00000000 Hyp Auxiliary Control Register. See 4.3.33 Auxiliary Control Register, EL2.
  c1 0 HCR RW 0x00000000 4.5.10 Hyp Configuration Register.
  1 HDCR RW 0x00000006d 4.5.12 Hyp Debug Control Register.
  2 HCPTR RW 0x000033FF 4.5.13 Hyp Architectural Feature Trap Register.
  3 HSTR RW 0x00000000 Hyp System Trap Register. See 4.3.36 Hypervisor System Trap Register.
  4 HCR2 RW 0x00000000 4.5.11 Hyp Configuration Register 2.
  7 HACR RW 0x00000000 4.3.37 Hyp Auxiliary Configuration Register.
a The reset value depends on primary input, CFGEND. The value shown assumes this signal is set to zero.
b See the ARM® Architecture Reference Manual ARMv8 for more information.
c RO at EL2 and EL0(NS).
d The reset value for bit[7] is UNK.
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