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ARM® Cortex®-A72 MPCore Processor Technical Reference ManualRevision r0p2
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4.4.4 c3 registers

The following table shows the System registers when CRn is c3 and the processor is in AArch32 state.

Table 4-87 c3 register summary

op1 CRm op2 Name Type Reset Description
0 c0 0 DACR RW UNK Domain Access Control Register, see the ARM® Architecture Reference Manual ARMv8
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