4.4.10 c9 registers

The following table shows the System registers when CRn is c9 and the processor is in AArch32 state.

Table 4-93 c9 register summary

op1 CRm op2 Name Type Reset Description
0 c12 0 PMCR RW 0x41023000 Performance Monitors Control Register. See 11.4.1 Performance Monitors Control Register, EL0.
  1 PMCNTENSET RW UNK Performance Monitors Count Enable Set Register. 
  2 PMCNTENCLR RW UNK Performance Monitors Count Enable Clear Register. a
  3 PMOVSR RW UNK Performance Monitors Overflow Flag Status Register. a
  4 PMSWINC WO - Performance Monitors Software Increment Register. a
  5 PMSELR RW UNK Performance Monitors Event Counter Selection Register. a
  6 PMCEID0 RO 0x7FFF0F3F Performance Monitors Common Event Identification Register 0. See 11.4.2 Performance Monitors Common Event Identification Register 0, EL0.
  7 PMCEID1 RO 0x00000000 Performance Monitors Common Event Identification Register 1. a
  c13 0 PMCCNTR RW UNK Performance Monitors Cycle Counter Register. a
  1 PMXEVTYPER RW UNK Performance Monitors Selected Event Type Register. a
  PMCCFILTR RW 0x00000000 Performance Monitors Cycle Count Filter Register. a
  2 PMXEVCNTR RW UNK Performance Monitors Selected Event Count Register. a
  c14 0 PMUSERENR RW 0x00000000 Performance Monitors User Enable Register. a
  1 PMINTENSET RW UNK Performance Monitors Interrupt Enable Set Register. a
  2 PMINTENCLR RW UNK Performance Monitors Interrupt Event Clear Register. a
  3 PMOVSSET RW UNK Performance Monitors Overflow Flag Status Set Register. a
1 c0 2 L2CTLR RW 0x00000000b L2 Control Register. See 4.3.58 L2 Control Register, EL1.
  3 L2ECTLR RW 0x00000000 L2 Extended Control Register. See 4.3.59 L2 Extended Control Register, EL1.
a See the ARM® Architecture Reference Manual ARMv8 for more information.
b The reset value depends on the processor implementation and the state of the L2RSTDISABLE signal.
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