ARM Cortex-A72 MPCore Processor Technical Reference Manual : 4.4.12 c12 registers

4.4.12 c12 registers

The following table shows the System registers when CRn is c12 and the processor is in AArch32 state.

Table 4-95 c12 register summary

op1	CRm	op2	Name	Type	Reset	Description
0	c0	0	VBAR	RW	`0x00000000`^a	Vector Base Address Register.
		1	MVBAR	RW	UNK	Monitor Vector Base Address Register. ^b
		2	RMR	RW	`0x00000000`^c	Reset Management Register. See 4.3.61 Reset Management Register, EL3.
	c1	0	ISR	RO	UNK	Interrupt Status Register. ^b
4	c0	0	HVBAR	RW	UNK	Hyp Vector Base Address Register. ^b

^a The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.

^b See the ARM^® Architecture Reference Manual ARMv8 for more information.

^c The reset value of bit[0] depends on the AA64nAA32 signal. The following table assumes this signal is LOW.

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