4.4.25 Miscellaneous operations

The following table shows the System instructions and the registers for miscellaneous operations in AArch32 state.

Table 4-109 Miscellaneous System operations

Name CRn op1 CRm op2 Type Reset Description
CP15ISB c7 4 c5 4 - UNK Instruction Synchronization Barrier operation, this operation is deprecated in ARMv8-A
CP15DSB   c10 4 - UNK Data Synchronization Barrier operation, this operation is deprecated in ARMv8-A
CP15DMB     5 - UNK Data Memory Barrier operation, this operation is deprecated in ARMv8-A
TPIDRURW c13 0 c0 2 RW UNK User Read/Write Thread ID Register 
TPIDRURO     3 RW b UNK EL1 only Thread ID Register a
TPIDRPRW     4 RW UNK Hyp Software Thread ID Register a
HTPIDR   4 c0 2 RW UNK User Read-Only Thread ID Register a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
b RO at EL0.
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