4.4.27 Security registers

The following table shows the 32-bit wide Security registers in AArch32 state.

Table 4-111 Security registers

Name CRn op1 CRm op2 Type Reset Description
SCR c1 0 c1 0 RW 0x00000000 4.5.7 Secure Configuration Register
SDER     1 RW 0x00000000 Secure Debug Enable Register 
NSACR     2 RW 0x00000000 4.5.8 Non-secure Access Control Register
SDCR     c3 1 RW 0x00000000 4.5.9 Secure Debug Configuration Register
VBAR c12 0 c0 0 RW 0x00000000b Vector Base Address Register a
MVBAR     1 RW UNK Monitor Vector Base Address Register a
ISR   c1 0 RO UNK Interrupt Status Register a
a See the ARM® Architecture Reference Manual ARMv8 for more information.
b The reset value is 0x00000000 for the Secure copy of the register. You must program the Non-secure copy of the register with the required initial value, as part of the processor boot sequence.
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