4.4.31 Implementation defined registers

The following table shows the IMPLEMENTATION DEFINED registers in AArch32 state. These registers provide test features and any required configuration options specific to the Cortex-A72 processor.

Table 4-114 IMPLEMENTATION DEFINED registers

Name CRn op1 CRm op2 Type Reset Width Description
AIDR c0 1 c0 7 - 0x00000000 32-bit Auxiliary ID Register. See 4.3.24 Auxiliary ID Register, EL1.
ACTLR c1 0 c0 1 - 0x00000000 32-bit Auxiliary Control Register. See 4.3.39 Auxiliary Control Register, EL3.
HACTLR 4 c0 1 RW 0x00000000 32-bit Hyp Auxiliary Control Register. See 4.3.33 Auxiliary Control Register, EL2.
HADFSR c5 4 c1 0 RW UNK 32-bit Hyp Auxiliary Data Fault Status Register. See 4.3.52 Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register.
HAIFSR     1 RW UNK 32-bit Hyp Auxiliary Instruction Fault Status Register. See 4.3.52 Auxiliary Fault Status Register 0, EL2 and Hyp Auxiliary Data Fault Status Register.
L2CTLR c9 1 c0 2 RW 0x00000000a 32-bit L2 Control Register. See 4.3.58 L2 Control Register, EL1.
L2ECTLR     3 RW 0x00000000 32-bit L2 Extended Control Register. See 4.3.59 L2 Extended Control Register, EL1.
AMAIR0 c10 0 c3 0 RW UNK 32-bit Auxiliary Memory Attribute Indirection Register 0. See 4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
AMAIR1     1 RW UNK 32-bit Auxiliary Memory Attribute Indirection Register 1. See 4.3.56 Auxiliary Memory Attribute Indirection Register, EL1 and EL3.
HAMAIR0     0 RW UNK 32-bit Hyp Auxiliary Memory Attribute Indirection Register 0. See 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2.
HAMAIR1     1 RW UNK 32-bit Hyp Auxiliary Memory Attribute Indirection Register 1. See 4.3.57 Auxiliary Memory Attribute Indirection Register, EL2.
IL1DATA0 c15 0 c0 0 RW UNK 32-bit 4.3.62 Instruction L1 Data n Register, EL1.
IL1DATA1     1
IL1DATA2     2
IL1DATA3     3
DL1DATA0     c1 0 RW UNK 32-bit 4.3.63 Data L1 Data n Register, EL1.
DL1DATA1     1
DL1DATA2     2
DL1DATA3     3
DL1DATA4     4
RAMINDEX     c4 0 WO - 32-bit 4.3.64 RAM Index operation.
L2ACTLR   1 c0 0 RW 0x00000010b 32-bit L2 Auxiliary Control Register. See .
CBAR   4 c0 0 RO -c 32-bit 4.5.24 Configuration Base Address Register>.
CPUACTLR - 0 c15 - RW -d 64-bit CPU Auxiliary Control Register. See 4.3.66 CPU Auxiliary Control Register, EL1.
CPUECTLR - 1 - RW -e 64-bit CPU Extended Control Register. See 4.3.67 CPU Extended Control Register, EL1.
CPUMERRSR - 2 - RW - 64-bit CPU Memory Error Syndrome Register. See 4.3.68 CPU Memory Error Syndrome Register, EL1.
L2MERRSR - 3 - RW -f 64-bit L2 Memory Error Syndrome Register. See 4.3.69 L2 Memory Error Syndrome Register, EL1.
a The reset value depends on the processor implementation and the state of the L2RSTDISABLE signal.
b The reset value is 0x00000010 for an ACE interface and 0x00004018 for a CHI interface.
c The reset value depends on the primary input, PERIPHBASE[43:18].
d The reset value is zero.
e The reset value is 0x0000 001B 0000 0000.
f The reset value for bits[63,47:40,39:32,31] is zero.
Non-ConfidentialPDF file icon PDF versionARM 100095_0002_03_en
Copyright © 2014, 2015 ARM. All rights reserved.