4.5.3 Multiprocessor Affinity Register

The MPIDR characteristics are:
Purpose
Provides an additional core identification mechanism for scheduling purposes in a cluster.
Usage constraints
The accessibility to the MPIDR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
Configurations
The MPIDR is:
  • Common to Secure and Non-secure states.
  • Architecturally mapped to the AArch64 MPIDR_EL1[31:0] register.
Attributes
See the register summary in Table 4-84 c0 register summary.
The following figure shows the MPIDR bit assignments.
Figure 4-80 MPIDR bit assignments
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The following table shows the MPIDR bit assignments.

Table 4-116 MPIDR bit assignments

Bits Name Function
[31] - Reserved, RES1.
[30] U
Indicates a single processor system, as distinct from core 0 in a cluster. This value is:
0Processor is part of a multicore system.
[29:25] - Reserved, RES0.
[24] MT
Indicates whether the lowest level of affinity consists of logical cores that are implemented using a multi-threading type approach:
0Performance of cores at the lowest affinity level is largely independent.
1Performance of cores at the lowest affinity level is very interdependent.
[23:16] Cluster ID Aff2 Indicates the value read in at reset, from the CLUSTERIDAFF2 configuration signal. It identifies a Cortex-A72 device in a system with more than one Cortex-A72 device present.
[15:8] Cluster ID Aff1 Indicates the value read in at reset, from the CLUSTERIDAFF1 configuration signal. It identifies a Cortex-A72 device in a system with more than one Cortex-A72 device present.
[7:2] - Reserved, RES0.
[1:0] CPU ID
Indicates the core number in the Cortex-A72 device. The possible values are:
0x0An MPCore device with one core only.
0x0, 0x1A Cortex-A72 device with two cores.
0x0, 0x1, 0x2A Cortex-A72 device with three cores.
0x0, 0x1, 0x2, 0x3A Cortex-A72 device with four cores.
To access the MPIDR in AArch32 state, read the CP15 registers with:
MRC p15, 0, <Rt>, c0, c0, 5; Read Multiprocessor Affinity Register
Related information
4.3.2 Multiprocessor Affinity Register, EL1
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