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Defines the configuration of the current Security state. It specifies:
If EL3 is using AArch64, accesses to this register from Secure EL1 using AArch32 are trapped to EL3.
The accessibility to the SCR by Exception level is:
The SCR is a Restricted access register that exists only in the Secure state.
The SCR is mapped to the AArch64 SCR_EL3 register.
|Attributes||See the register summary in Table 4-85 c1 register summary.|
Table 4-120 SCR bit assignments
Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from Non-secure memory. The possible values are:
Hyp Call enable. This bit enables the use of
Secure Monitor Call disable. This bit causes the
A trap of the
Not Early Termination. This bit disables early termination.
This bit is not implemented, RES0.
A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state. For the Cortex-A72 processor:
F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state. For the Cortex-A72 processor:
External Abort handler. This bit controls which mode takes external aborts. The possible values are:
FIQ handler. This bit controls which mode takes FIQ exceptions. The possible values are:
IRQ handler. This bit controls which mode takes IRQ exceptions. The possible values are:
Non-secure bit. Except when the processor is in Monitor mode, this bit determines the Security state of the processor. The possible values are:
NoteWhen the processor is in Monitor mode, it is always in Secure state, regardless of the value of the NS bit.
MRC p15, 0, <Rt>, c1, c1, 0; Read Secure Configuration Register data MCR p15, 0, <Rt>, c1, c1, 0; Write Secure Configuration Register data