ARM Cortex-A72 MPCore Processor Technical Reference Manual : 4.5.10 Hyp Configuration Register

4.5.10 Hyp Configuration Register

The HCR characteristics are:

Purpose

Provides configuration controls for virtualization, including defining whether various Non-secure operations are trapped to Hyp mode.

Usage constraints

The accessibility to the HCR in AArch32 state by Exception level is:

EL0	EL1(NS)	EL1(S)	EL2	EL3(SCR.NS = 1)	EL3(SCR.NS = 0)
-	-	-	RW	RW	-

Configurations

The HCR is:

A Banked EL2 register
Architecturally mapped to the AArch64 HCR_EL2[31:0] register.

Attributes

See the register summary in Table 4-85 c1 register summary.

The following figure shows the HCR bit assignments.

Figure 4-87 HCR bit assignments

The following table shows the HCR bit assignments.

Table 4-123 HCR bit assignments

Bits Name Function

[31] - Reserved, RES0.

[30]

TRVM

Trap Read of Virtual Memory controls. When 1, this causes reads to the EL1 virtual memory control registers from EL1 to be trapped to EL2. This covers the following registers:

AArch32

SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.

The reset value is 0.

[29:28] - Reserved, RES0.

[27]

TGE

Trap general exceptions. When this bit is set to 1, and the processor is executing at EL0 in Non-secure state, Undefined Instruction exceptions, Supervisor Call exceptions, synchronous External aborts and some Alignment faults are taken in Hyp mode.

The SCTLR.M bit is treated as being 0 regardless of its actual state, other than for the purpose of reading the bit.

When the processor is executing at EL1 in Non-secure state, and this bit is set to 1, the Illegal Exception Return mechanism is invoked.

The reset value is 0.

[26]

TVM

Trap Virtual Memory controls. When 1, this causes writes to the EL1 virtual memory control registers from EL1 to be trapped to EL2. This covers the following registers:

AArch32

SCTLR, TTBR0, TTBR1, TTBCR, DACR, DFSR, IFSR, DFAR, IFAR, ADFSR, AIFSR, PRRR/MAIR0, NMRR/MAIR1, AMAIR0, AMAIR1, and CONTEXTIDR.

The reset value is 0.

[25]

TTLB

Trap TLB maintenance instructions. When 1, this causes TLB maintenance instructions executed from EL1 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:

AArch32 TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, ITLBIALL, DTLBIALL, TLBIALL, ITLBIMVA, DTLBIMVA, TLBIMVA, ITLBIASID, DTLBIASID, TLBIASID, TLBIMVAA, TLBIMVALIS, TLBIMVAALIS, TLBIMVAL, and TLBIMVAAL.

The reset value is 0.

[24]

TPU

Trap Cache maintenance instructions to Point of Unification. When 1, this causes Cache maintenance instructions to the point of unification executed from EL1 or EL0 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:

AArch32 ICIMVAU, ICIALLU, ICIALLUIS, and DCCMVAU.

The reset value is 0.

[23]

TPC

Trap Data/Unified Cache maintenance operations to Point of Coherency. When 1, this causes Data or Unified Cache maintenance instructions by address to the point of coherency executed from EL1 or EL0 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:

AArch32 DCIMVAC, DCCIMVAC, and DCCMVAC.

The reset value is 0.

[22]

TSW

Trap Data/Unified Cache maintenance operations by Set/Way. When 1, this causes Data or Unified Cache maintenance instructions by set/way executed from EL1 that are not UNDEFINED to be trapped to EL2. This covers the following instructions:

AArch32 DCISW, DCCSW, and DCCISW.

The reset value is 0.

[21]

TAC

Trap ACTLR accesses. When this bit is set to 1, any valid Non-secure access to the ACTLR is trapped to Hyp mode.

The reset value is 0.

[20]

TIDCP

Trap Implementation Dependent functionality. When 1, this causes accesses to the following instruction set space executed from EL1 to be trapped to EL2:

AArch32

All CP15 MCR and MRC instructions as follows:

CRn is 9, op1 is 0-7, CRm is c0, c1, c2, c5, c6, c7, or c8, and op2 is 0-7.
CRn is 10, op1 is 0-7, CRm is c0, c1, c4, or c8, and op2 is 0-7.
CRn is 11, op1 is 0-7, CRm is c0 to c8, or c15, and op2 is 0-7.

The reset value is 0.

[19]

TSC

Trap SMC instruction. When this bit is set to 1, any attempt from Non-secure EL1 to execute an SMC instruction, that passes its condition check if it is conditional, is trapped to Hyp mode.

The reset value is 0.

[18]

TID3

Trap ID Group 3. When 1, this causes reads to the following registers executed from EL1 to be trapped to EL2:

AArch32

ID_PFR0, ID_PFR1, ID_DFR0, ID_AFR0, ID_MMFR0, ID_MMFR1, ID_MMFR2, ID_MMFR3, ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, ID_ISAR5, MVFR0, MVFR1, and MVFR2 and MRC instructions to the following locations:

op1 is 0, CRn is 0, CRm is c3, c4, c5, c6, or c7, and op2 is 0 or 1.
op1 is 0, CRn is 0, CRm is c3, and op2 is 2.
op1 is 0, CRn is 0, CRm is 5, and op2 is 4 or 5.

The reset value is 0.

[17]

TID2

Trap ID Group 2. When 1, this causes reads (or writes to CSSELR/CSSELR_EL1) to the following registers executed from EL1 or EL0 if not UNDEFINED to be trapped to EL2:

AArch32

CTR, CCSIDR, CLIDR, and CSSELR.

The reset value is 0.

[16]

TID1

Trap ID Group 1. When 1, this causes reads to the following registers executed from EL1 to be trapped to EL2:

AArch32

TCMTR, TLBTR, AIDR, and REVIDR.

The reset value is 0.

[15]

TID0

Trap ID Group 0. When 1, this causes reads to the following registers executed from EL1 or EL0 if not UNDEFINED to be trapped to EL2:

AArch32

FPSID and JIDR.

The reset value is 0.

[14]

TWE

Traps WFE instruction if it would cause suspension of execution. For example, if there is no pending WFE event:

0	`WFE` instruction is not trapped. This is the reset value.
1	`WFE` instruction executed in Non-secure EL1 or EL0 is trapped to EL2.

[13]

TWI

Traps WFI instruction if it would cause suspension of execution. For example, if there is no pending WFI event:

0	`WFI` instruction is not trapped. This is the reset value.
1	`WFI` instruction executed in Non-secure EL1 or EL0 is trapped to EL2.

[12]

Default Cacheable. When this bit is set to 1 the memory type and attributes determined by the stage 1 translation is Normal, Non-shareable, Inner Write-Back Write-Allocate, Outer Write-Back Write-Allocate.

When executing in a Non-secure mode other than Hyp mode and the HCR.DC bit is set, the processor behavior is consistent with the behavior when:

The SCTLR.M bit is clear, regardless of the actual value of the SCTLR.M bit.
- An explicit read of the SCTLR.M bit returns its actual value.
The HCR.VM bit is set, regardless of the actual value of the HCR.VM bit.
- An explicit read of the HCR.VM bit returns its actual value.

The reset value is 0.

[11:10]

BSU

Barrier Shareability upgrade. The value in this field determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0. The values are:

`0b00`	No effect.
`0b01`	Inner Shareable.
`0b10`	Outer Shareable.
`0b11`	Full System.

The reset value is 0.

[9]

Force broadcast. When 1, this causes the following instructions to be broadcast within the Inner Shareable domain when executed from Non-secure EL1:

AArch32 ITLBIALL, DTLBIALL, TLBIALL, ITLBIMVA, DTLBIMVA, TLBIMVA, ITLBIASID, DTLBIASID, TLBIASID, TLBIMVAA, BPIALL, and ICIALLU.

The reset value is 0.

[8]

Virtual Asynchronous Abort exception. Setting this bit signals a virtual Asynchronous Abort exception to the Guest OS, when the AMO bit is set to 1 and the processor is executing in Non-secure state at EL0 or EL1.

The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.

The reset value is 0.

[7]

Virtual IRQ exception. Setting this bit signals a virtual IRQ exception to the Guest OS, when the IMO bit is set to 1 and the processor is executing in Non-secure state at EL0 or EL1.

The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.

The reset value is 0.

[6]

Virtual FIQ exception. Setting this bit signals a virtual FIQ exception to the Guest OS, when the FMO bit is set to 1 and the processor is executing in Non-secure state at EL0 or EL1.

The Guest OS cannot distinguish the virtual exception from the corresponding physical exception.

The reset value is 0.

[5]

AMO

Asynchronous Abort Mask Override. When this bit is set to 1, it overrides the effect of CPSR.A, and enables virtual exception signaling by the VA bit.

The reset value is 0.

[4]

IMO

IRQ Mask Override. When this bit is set to 1, it overrides the effect of CPSR.I, and enables virtual exception signaling by the VI bit.

The reset value is 0.

[3]

FMO

FIQ Mask Override. When this bit is set to 1, it overrides the effect of CPSR.F, and enables virtual exception signaling by the VF bit.

The reset value is 0.

[2]

PTW

Protected Table Walk. When 1, if the stage 2 translation of a translation table access made as part of a stage 1 translation table walk at Non-secure EL0 or EL1 maps that translation table access to Device memory, the access is faulted as a stage 2 Permission fault.

The reset value is 0.

[1]

SWIO

Set/Way Invalidation Override. When 1, this causes EL1 execution of the Data Cache Invalidate by Set/Way instruction to be treated as Data Cache Clean and Invalidate by Set/Way. The affected instructions are:

AArch32 DCISW is executed as DCCISW.

The reset value is 0.

[0]

Second stage of Translation enable. When 1, this enables the second stage of translation for execution in EL1 and EL0. This bit is permitted to be cached in a TLB.

The reset value is 0.

To access the HCR in AArch32 state, read or write the CP15 register with:

MRC p15, 4, <Rt>, c1, c1, 0; Read Hyp Configuration Register
MCR p15, 4, <Rt>, c1, c1, 0; Write Hyp Configuration Register

Related information

4.3.34 Hypervisor Configuration Register, EL2

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