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Home > System Control > AArch32 register descriptions > Hyp Configuration Register |
Purpose | Provides configuration controls for virtualization, including defining whether various Non-secure operations are trapped to Hyp mode. | ||||||||||||
Usage constraints | The accessibility to the HCR in AArch32 state by Exception level is:
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Configurations | The HCR is:
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Attributes | See the register summary in Table 4-85 c1 register summary. |
Table 4-123 HCR bit assignments
Bits | Name | Function | ||||||||
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[31] | - | Reserved, RES0. | ||||||||
[30] | TRVM |
Trap Read of Virtual Memory controls. When 1, this causes reads
to the EL1 virtual memory control registers from EL1 to be trapped to EL2. This
covers the following registers:
The reset value is 0.
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[29:28] | - | Reserved, RES0. | ||||||||
[27] | TGE |
Trap general exceptions. When this bit is set to 1, and the
processor is executing at EL0 in Non-secure state, Undefined Instruction
exceptions, Supervisor Call exceptions, synchronous External aborts and some
Alignment faults are taken in Hyp mode.
The SCTLR.M bit is treated as being 0 regardless of its actual
state, other than for the purpose of reading the bit.
When the processor is executing at EL1 in Non-secure state, and
this bit is set to 1, the Illegal Exception Return mechanism is invoked.
The reset value is 0.
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[26] | TVM |
Trap Virtual Memory controls. When 1, this causes writes to the
EL1 virtual memory control registers from EL1 to be trapped to EL2. This covers
the following registers:
The reset value is 0.
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[25] | TTLB |
Trap TLB maintenance instructions. When 1, this causes TLB
maintenance instructions executed from EL1 that are not UNDEFINED to be trapped to EL2. This covers the
following instructions:
The reset value is 0.
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[24] | TPU |
Trap Cache maintenance instructions to Point of Unification.
When 1, this causes Cache maintenance instructions to the point of unification
executed from EL1 or EL0 that are not UNDEFINED to be trapped to EL2. This covers the
following instructions:
The reset value is 0.
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[23] | TPC |
Trap Data/Unified Cache maintenance operations to Point of
Coherency. When 1, this causes Data or Unified Cache maintenance instructions by
address to the point of coherency executed from EL1 or EL0 that are not UNDEFINED to be trapped to EL2.
This covers the following instructions:
The reset value is 0.
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[22] | TSW |
Trap Data/Unified Cache maintenance operations by Set/Way. When
1, this causes Data or Unified Cache maintenance instructions by set/way executed
from EL1 that are not UNDEFINED to be trapped to EL2. This covers the following
instructions:
The reset value is 0.
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[21] | TAC |
Trap ACTLR accesses. When this bit is set to 1, any valid
Non-secure access to the ACTLR is trapped to Hyp mode.
The reset value is 0.
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[20] | TIDCP |
Trap Implementation Dependent functionality. When 1, this causes
accesses to the following instruction set space executed from EL1 to be trapped to
EL2:
The reset value is 0.
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[19] | TSC |
Trap
SMC instruction. When
this bit is set to 1, any attempt from Non-secure EL1 to execute an SMC instruction, that passes its condition check if it
is conditional, is trapped to Hyp mode.The reset value is 0.
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[18] | TID3 |
Trap ID Group 3. When 1, this causes reads to the following
registers executed from EL1 to be trapped to EL2:
The reset value is 0.
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[17] | TID2 |
Trap ID Group 2. When 1, this causes reads (or writes to
CSSELR/CSSELR_EL1) to the following registers executed from EL1 or EL0 if not
UNDEFINED to be trapped to
EL2:
The reset value is 0.
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[16] | TID1 |
Trap ID Group 1. When 1, this causes reads to the following
registers executed from EL1 to be trapped to EL2:
The reset value is 0.
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[15] | TID0 |
Trap ID Group 0. When 1, this causes reads to the following
registers executed from EL1 or EL0 if not UNDEFINED to be trapped to EL2:
The reset value is 0.
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[14] | TWE |
Traps
WFE instruction if it
would cause suspension of execution. For example, if there is no pending WFE
event:
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[13] | TWI |
Traps
WFI instruction if it
would cause suspension of execution. For example, if there is no pending WFI
event:
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[12] | DC |
Default Cacheable. When this bit is set to 1 the memory type and
attributes determined by the stage 1 translation is Normal, Non-shareable, Inner
Write-Back Write-Allocate, Outer Write-Back Write-Allocate.
When executing in a Non-secure mode other than Hyp mode and the
HCR.DC bit is set, the processor behavior is consistent with the behavior
when:
The reset value is 0.
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[11:10] | BSU |
Barrier Shareability upgrade. The value in this field determines
the minimum shareability domain that is applied to any barrier executed from EL1
or EL0. The values are:
The reset value is 0.
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[9] | FB |
Force broadcast. When 1, this causes the following instructions
to be broadcast within the Inner Shareable domain when executed from Non-secure
EL1:
The reset value is 0.
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[8] | VA |
Virtual Asynchronous Abort exception. Setting this bit signals a
virtual Asynchronous Abort exception to the Guest OS, when the AMO bit is set to 1
and the processor is executing in Non-secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the
corresponding physical exception.
The reset value is 0.
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[7] | VI |
Virtual IRQ exception. Setting this bit signals a virtual IRQ
exception to the Guest OS, when the IMO bit is set to 1 and the processor is
executing in Non-secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the
corresponding physical exception.
The reset value is 0.
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[6] | VF |
Virtual FIQ exception. Setting this bit signals a virtual FIQ
exception to the Guest OS, when the FMO bit is set to 1 and the processor is
executing in Non-secure state at EL0 or EL1.
The Guest OS cannot distinguish the virtual exception from the
corresponding physical exception.
The reset value is 0.
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[5] | AMO |
Asynchronous Abort Mask Override. When this bit is set to 1, it
overrides the effect of CPSR.A, and enables virtual exception signaling by the VA
bit.
The reset value is 0.
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[4] | IMO |
IRQ Mask Override. When this bit is set to 1, it overrides the
effect of CPSR.I, and enables virtual exception signaling by the VI bit.
The reset value is 0.
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[3] | FMO |
FIQ Mask Override. When this bit is set to 1, it overrides the
effect of CPSR.F, and enables virtual exception signaling by the VF bit.
The reset value is 0.
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[2] | PTW |
Protected Table Walk. When 1, if the stage 2 translation of a
translation table access made as part of a stage 1 translation table walk at
Non-secure EL0 or EL1 maps that translation table access to Device memory, the
access is faulted as a stage 2 Permission fault.
The reset value is 0.
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[1] | SWIO |
Set/Way Invalidation Override. When 1, this causes EL1 execution
of the Data Cache Invalidate by Set/Way instruction to be treated as Data Cache
Clean and Invalidate by Set/Way. The affected instructions are:
The reset value is 0.
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[0] | VM |
Second stage of Translation enable. When 1, this enables the
second stage of translation for execution in EL1 and EL0. This bit is permitted to
be cached in a TLB.
The reset value is 0.
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MRC p15, 4, <Rt>, c1, c1, 0; Read Hyp Configuration Register MCR p15, 4, <Rt>, c1, c1, 0; Write Hyp Configuration Register