4.5.18 Physical Address Register

The PAR characteristics are:
Purpose
Receives the PA from any address translation operation.
Usage constraints
The accessibility to the PAR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Configurations
The PAR is Banked for the Secure and Non-secure states.
The Non-secure PAR is architecturally mapped to AArch64 PAR_EL1 register.
The PAR[63:32] is RES0 when using the Short-descriptor translation format.
Attributes
The processor does not use any IMPLEMENTATION DEFINED bits in the 32-bit or 64-bit format PAR or the PAR_EL1, so these bits are RES0.
See the register summary in Table 4-90 c7 register summary.
See the ARM® Architecture Reference Manual ARMv8 for more information.
To access the PAR in AArch32 state when using the Short-descriptor translation format, read or write the CP15 register with:
MRC p15, 0, <Rt>, c7, c4, 0; Read Physical Address Register
MCR p15, 0, <Rt>, c7, c4, 0; Write Physical Address Register
To access the PAR in AArch32 state when using the Long-descriptor translation format, read or write the CP15 register with:
MRRC p15, 0, <Rt>, <Rt2>, c7; Read Physical Address Register
MCRR p15, 0, <Rt>, <Rt2>, c7; Write Physical Address Register
Related information
4.3.55 Physical Address Register, EL1
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