4.5.21 Normal Memory Remap Register.

The NMRR characteristics are:
Purpose
Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in the PRRR.
Usage constraints
The accessibility to the NMRR by Exception level is:
EL0 EL1(NS) EL1(S) EL2 EL3(SCR.NS = 1) EL3(SCR.NS = 0)
- RW RW RW RW RW
Write access to the Secure copy of NMRR is disabled when the CP15SDISABLE signal is HIGH.
Configurations
The NMRR is:
  • Banked for the Secure and Non-secure states.
  • Only relevant if the TTBCR.EAE bit is 0.
  • Architecturally mapped on to the MAIR1 register in AArch32 state.
The Non-secure NMRR is architecturally mapped to the AArch64 MAIR_EL1[63:32] register.
The Secure NMRR is mapped to the AArch64 MAIR_EL3[63:32] register.
Attributes
See the register summary in Table 4-94 c10 register summary.
See the ARM® Architecture Reference Manual ARMv8 for more information.
To access the NMRR in AArch32 state, read or write the CP15 register with:
MRC p15, 0, <Rt>, c10, c2, 1; Read Normal Memory Remap Register
MCR p15, 0, <Rt>, c10, c2, 1; Write Normal Memory Remap Register
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