The L1 instruction TLB is a 48-entry fully-associative structure.
This TLB caches entries of three different page sizes, natively
4KB, 64KB, and 1MB, of VA to PA mappings. If the page tables map
the memory region to a larger granularity than 1MB, it only allocates
one mapping for the particular 1MB region to which the current access
A hit in the instruction TLB provides a single CLK cycle
access to the translation, and returns the PA to the instruction
cache for comparison. It also checks the access permissions to signal
a Prefetch Abort.