6.3.5 Parity error handling

The instruction cache implements one parity bit per 16-bits of instruction data. The instruction cache Tag array is also protected by two parity bits per tag entry. Parity errors invalidate the offending cache line, and force a fetch from the L2 cache on the next access. No aborts are generated on parity errors that occur within the instruction cache. The location of a parity error is reported in the CPU Memory Error Syndrome Register. Because the data cache shares this register, there is no guarantee that this register contains the location of the last instruction side parity error.
Related information
4.3.68 CPU Memory Error Syndrome Register, EL1
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