6.4 L1 data memory system

The L1 data memory system executes all memory operations in the Cortex-A72 processor.

In addition, it handles cache maintenance operations, TLB maintenance operations, and exclusive operations using the Load-Exclusive, Store-Exclusive and Clear-Exclusive instructions.
The L1 memory system supports out-of-order execution of instructions. Loads can be executed and return their data while they are still speculative and might be flushed. Stores can be executed, but not committed to memory, while they are still speculative. Speculative loads can forward data from older speculative stores.
The L1 memory system is non-blocking and supports hit-under-miss. For Normal memory, up to six 64-byte cache line requests can be outstanding at a time. While those requests are waiting for memory, loads to different cache lines can hit the cache and return their data.
The L1 data memory system includes the following:
  • L1 data cache.
  • Address generation logic.
  • The L1 TLB.
  • Buffering for stores that have not been written to the cache or memory.
  • Fill buffers for processing cache line fills and Non-cacheable reads.
  • Coherence logic for handling snoop requests.
  • Hardware prefetch logic.
This section contains the following subsections:
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