The multiprocessor supports the
PRFM prefetch hint instructions.
For Normal Write-Back Cacheable memory page, the
PRFM L1 instructions cause the line
to be allocated to the L1 data cache of the executing processor.
PLD instruction brings the line into the
cache in Exclusive or Shared state and the
brings the line into the cache in Exclusive state. The preload instruction
PLDI, is treated as a
PLDW instructions are
performance hints instructions only and might be dropped in some